[PATCH] D14141: [1/4] SP and PC as shifted-reg operands are unpredictable in ARMv7 Thumb

[Renato Golin via llvm-commits]

rengolin added inline comments.

================
Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:8534
@@ -8532,12 +8533,3 @@
   }
-  // Some high-register supporting Thumb1 encodings only allow both registers
-  // to be from r0-r7 when in Thumb2.
-  else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
-           isARMLowRegister(Inst.getOperand(1).getReg()) &&
-           isARMLowRegister(Inst.getOperand(2).getReg()))
-    return Match_RequiresThumb2;
-  // Others only require ARMv6 or later.
-  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
-           isARMLowRegister(Inst.getOperand(0).getReg()) &&
-           isARMLowRegister(Inst.getOperand(1).getReg()))
-    return Match_RequiresV6;
+  else if (isThumbOne()) {
+    // Some high-register supporting Thumb1 encodings only allow both registers
----------------
    } else if (...) {

================
Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:8656
@@ -8642,1 +8655,3 @@
+  case Match_RequiresV8:
+    return Error(IDLoc, "using SP in this instruction requires ARMv8 or later");
   case Match_ImmRange0_15: {
----------------
This seems an awfully specific error message to this generic error.

So far, the only use in for SP, but if someone re-uses it for something else, the error message will be completely bogus.

================
Comment at: test/MC/ARM/thumb2-diagnostics.s:95
@@ +94,3 @@
+
+        @ PC is not valid as shifted-rGPR
+        sbc.w r2, r7, pc, lsr #16
----------------
Also add a test for SP on ARMv8.


http://reviews.llvm.org/D14141