[PATCH] D13922: Restrict tail duplication in the presence of subregisters

[Krzysztof Parzyszek via llvm-commits]

kparzysz created this revision.
kparzysz added a reviewer: echristo.
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kparzysz set the repository for this revision to rL LLVM.

Tail duplication can be confused by subregisters in phi nodes.  The Hexagon testcase leads to an abort without this fix.

Repository:
  rL LLVM

http://reviews.llvm.org/D13922

Files:
  lib/CodeGen/TailDuplication.cpp
  test/CodeGen/Hexagon/tail-dup-subreg-abort.ll

Index: test/CodeGen/Hexagon/tail-dup-subreg-abort.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Hexagon/tail-dup-subreg-abort.ll
@@ -0,0 +1,28 @@
+; RUN: llc -march=hexagon -O2 -disable-cgp < %s
+; REQUIRES: asserts
+;
+; Tail duplication can ignore subregister information on PHI nodes, and as
+; a result, generate COPY instructions between registers of different classes.
+; This could lead to HexagonInstrInfo::copyPhysReg aborting on an unhandled
+; src/dst combination.
+;
+define i32 @foo(i32 %x, i64 %y) nounwind {
+entry:
+  %a = icmp slt i32 %x, 0
+  %lo = trunc i64 %y to i32
+  br i1 %a, label %next, label %tail
+tail:
+  br label %join
+next:
+  %c = icmp eq i32 %x, 0
+  br i1 %c, label %b1, label %tail
+b1:
+  %t1 = lshr i64 %y, 32
+  %hi = trunc i64 %t1 to i32
+  br label %join
+join:
+  %val = phi i32 [ %hi, %b1 ], [ %lo, %tail ]
+  ret i32 %val
+}
+
+
Index: lib/CodeGen/TailDuplication.cpp
===================================================================
--- lib/CodeGen/TailDuplication.cpp
+++ lib/CodeGen/TailDuplication.cpp
@@ -607,6 +607,20 @@
       return false;
   }
 
+  // Check if any of the successors of TailBB has a PHI node in which the
+  // value corresponding to TailBB uses a subregister.
+  for (auto SB : TailBB.successors()) {
+    for (auto &I : *SB) {
+      if (!I.isPHI())
+        break;
+      unsigned Idx = getPHISrcRegOpIdx(&I, &TailBB);
+      assert(Idx != 0);
+      MachineOperand &PU = I.getOperand(Idx);
+      if (PU.getSubReg() != 0)
+        return false;
+    }
+  }
+
   if (HasIndirectbr && PreRegAlloc)
     return true;
 


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