[PATCH] D13771: [AArch64]Add support for converting halfword loads into a 32-bit word load

[James Molloy via llvm-commits]

Hi Jun,

I'm concerned about the performance portability of this change. It takes N
loads (which are contiguous so would all hit the cache) and converts to N+1
operations. I'm concerned that the gain might be microarchitectural and
should be gated on a subtarget feature. What targets did you test this on?
How did the test-suite respond?

Cheers,

James

On Mon, 19 Oct 2015 at 19:39 Jun Bum Lim via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> junbuml closed this revision.
> junbuml added a comment.
>
> Committed in r250719
>
>
> http://reviews.llvm.org/D13771
>
>
>
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