[PATCH] D13771: [AArch64]Add support for converting halfword loads into a 32-bit word load

[Chad Rosier via llvm-commits]

mcrosier accepted this revision.
mcrosier added a comment.
This revision is now accepted and ready to land.

LGTM, with one minor nit.


================
Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:1142
@@ +1141,3 @@
+  if (Paired != E) {
+    ++NumPairCreated;
+    if (isUnscaledLdSt(MI))
----------------
If we merge two ldrh instructions into a ldr we haven't actually created a paired instruction.  How about we add another statistic to count when we merge narrow loads/stores into wider loads/stores?


http://reviews.llvm.org/D13771