[PATCH] D13593: [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used

[Jelena Losic via llvm-commits]

Jelena.Losic added a comment.

Test implementation given in the patch is able to detect situation when pre-R6 opcode is generated for sc instruction.
Object code is generated by llc, disassembled by llvm-objdump (command line option -mattr=+mips64r6 is used) and llvm-objdump output is searched (by using grep - it is used in Object tests) for occurrence of sc mnemonic.
Because -mattr=+mips64r6 option is used llvm-objdump is not able to disassemble pre-R6 instruction opcodes and reports warning instead of instruction mnemonic.

llvm-objdump output - WITHOUT patch applied:
Disassembly of section .text:
atomic_load_test:

  0:     f0 ff bd 67            daddiu  $sp, $sp, -16
  4:     08 00 a3 df           ld            $3, 8($sp)
  8:     00 00 04 24          addiu     $4, $zero, 0

llvm/llvm2/build/bin/llvm-objdump: warning: invalid instruction encoding <-  without patch opcode is not recognized

  10:    05 00 44 14          bne        $2, $4, 24
  14:    00 00 00 00          nop
  18:    00 00 05 24          addiu     $5, $zero, 0

llvm/llvm2/build/bin/llvm-objdump: warning: invalid instruction encoding <-  without patch opcode is not recognized

  20:    fa ff a0 10            beqz      $5, -20
  24:    00 00 00 00          nop
  28:    0f 00 00 00           sync
  2c:    04 00 a2 af           sw          $2, 4($sp)
  30:    09 00 e0 03          jr             $ra
  34:    10 00 bd 67          daddiu  $sp, $sp, 16
   

llvm-objdump output - WITH patch applied:
Disassembly of section .text:
atomic_load_test:

   0:     f0 ff bd 67            daddiu  $sp, $sp, -16
   4:     08 00 a3 df           ld            $3, 8($sp)
   8:     00 00 04 24          addiu     $4, $zero, 0
   c:      36 00 62 7c           ll              $2, 0($3)
  10:    05 00 44 14          bne        $2, $4, 24
  14:    00 00 00 00          nop
  18:    00 00 05 24          addiu     $5, $zero, 0
  1c:    26 00 65 7c           sc            $5, 0($3)                   <- with patch opcode is recognized
  20:    fa ff a0 10            beqz      $5, -20
  24:    00 00 00 00          nop
  28:    0f 00 00 00           sync
  2c:    04 00 a2 af           sw          $2, 4($sp)
  30:    09 00 e0 03          jr             $ra
  34:    10 00 bd 67          daddiu  $sp, $sp, 16            
   

Is it OK with you if I move test in CodeGen and modify it to use FileCheck instead of grep or some other approach is needed to check generated opcodes?
Having in mind that existing (non micromips) atomic tests do not check instruction opcodes is it OK to create new test in this case?

I will add checks for ll, lld and scd opcodes.


http://reviews.llvm.org/D13593