[llvm] r250033 - [ARM] Mark Swift MISched model as incomplete

[James Molloy via llvm-commits]

Author: jamesm
Date: Mon Oct 12 07:49:59 2015
New Revision: 250033

URL: http://llvm.org/viewvc/llvm-project?rev=250033&view=rev
Log:
[ARM] Mark Swift MISched model as incomplete

The Swift Machine Scheduler Model is incomplete. There are instructions
missing which can trigger the "incomplete machine model" abort. This was
observed when a downstream SchedMachineModel was added to the ARM
target.

Patch by Christof Douma!

Modified:
    llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td?rev=250033&r1=250032&r2=250033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td Mon Oct 12 07:49:59 2015
@@ -43,6 +43,7 @@ def SwiftModel : SchedMachineModel {
   let MicroOpBufferSize = 45; // Based on NEON renamed registers.
   let LoadLatency = 3;
   let MispredictPenalty = 14; // A branch direction mispredict.
+  let CompleteModel = 0;      // FIXME: Remove if all instructions are covered.
 }
 
 // Swift predicates.