[PATCH] D13527: AMDGPU: Exclude SGPRs except m0 from movrel operands

[Tom Stellard via llvm-commits]

tstellarAMD added a comment.

I've seen scheduler changes like this before.  I think adding the new register class affects the register pressure analysis.


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Comment at: lib/Target/AMDGPU/SIInstructions.td:1344-1346
@@ -1343,5 +1343,5 @@
 let Uses = [M0, EXEC] in {
-defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>;
-defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>;
-defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>;
+defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32_M0>;
+defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32_M0>;
+defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32_M0>;
 } // End Uses = [M0, EXEC]
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Using M0 as src1, is only possible for V_MOVERELD_B32, because the other two use src1 as the base register and aren't actually reading values from it.




http://reviews.llvm.org/D13527