[PATCH] D13442: [AArch64] Fold vector fmul by pow2 into floating-point to fixed-point conversion.

[Tim Northover via llvm-commits]

t.p.northover added a comment.

Hi Chad,

I think the bulk of the logic's fine, just one or two cleanups...


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7537-7538
@@ +7536,4 @@
+// elements are the same constant, C, and Log2(C) ranges from 1 to Range.
+static bool isConstVecPow2(SDValue ConstVec, bool IsSigned, uint64_t &C,
+                           unsigned Range) {
+  integerPart CN;
----------------
I think this function could be made simpler (and more generic, e.g. handling undefs too) by calling BuildVectorSDNode::isConstantSplat.

================
Comment at: test/CodeGen/AArch64/fcvt_combine.ll:5
@@ +4,3 @@
+; CHECK-NOT: fmul.2s
+; CHECK: fcvtzs.2s
+; CHECK: ret
----------------
This style doesn't check that the fixed-point shift is correctly translated.


Repository:
  rL LLVM

http://reviews.llvm.org/D13442