[llvm] r249015 - [SystemZ] Add assembly instructions for obtaining clock values as well as CPU features
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 1 07:43:49 PDT 2015
Author: uweigand
Date: Thu Oct 1 09:43:48 2015
New Revision: 249015
URL: http://llvm.org/viewvc/llvm-project?rev=249015&view=rev
Log:
[SystemZ] Add assembly instructions for obtaining clock values as well as CPU features
Provide assembler support for STCK, STCKF, STCKE, and STFLE.
Author: joncmu
Differential Revision: http://reviews.llvm.org/D13299
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-good.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=249015&r1=249014&r2=249015&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Thu Oct 1 09:43:48 2015
@@ -1462,6 +1462,26 @@ let usesCustomInserter = 1 in {
let mayLoad = 1, Defs = [CC], Uses = [R0L] in
defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
+// Other instructions for inline assembly
+let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
+ def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2),
+ "stck\t$BD2",
+ []>;
+let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
+ def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2),
+ "stckf\t$BD2",
+ []>;
+let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
+ def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2),
+ "stcke\t$BD2",
+ []>;
+let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
+ def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2),
+ "stfle\t$BD2",
+ []>;
+
+
+
//===----------------------------------------------------------------------===//
// Peepholes.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=249015&r1=249014&r2=249015&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Thu Oct 1 09:43:48 2015
@@ -7537,7 +7537,79 @@
# CHECK: stcy %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x72
-# CHECK: stcy %r0, -1
+# CHECK: stck 0
+0xb2 0x05 0x00 0x00
+
+# CHECK: stck 0(%r1)
+0xb2 0x05 0x10 0x00
+
+#CHECK: stck 0(%r15)
+0xb2 0x05 0xf0 0x00
+
+#CHECK: stck 4095
+0xb2 0x05 0x0f 0xff
+
+#CHECK: stck 4095(%r1)
+0xb2 0x05 0x1f 0xff
+
+#CHECK: stck 4095(%r15)
+0xb2 0x05 0xff 0xff
+
+# CHECK: stckf 0
+0xb2 0x7c 0x00 0x00
+
+# CHECK: stckf 0(%r1)
+0xb2 0x7c 0x10 0x00
+
+#CHECK: stckf 0(%r15)
+0xb2 0x7c 0xf0 0x00
+
+#CHECK: stckf 4095
+0xb2 0x7c 0x0f 0xff
+
+#CHECK: stckf 4095(%r1)
+0xb2 0x7c 0x1f 0xff
+
+#CHECK: stckf 4095(%r15)
+0xb2 0x7c 0xff 0xff
+
+# CHECK: stcke 0
+0xb2 0x78 0x00 0x00
+
+# CHECK: stcke 0(%r1)
+0xb2 0x78 0x10 0x00
+
+#CHECK: stcke 0(%r15)
+0xb2 0x78 0xf0 0x00
+
+#CHECK: stcke 4095
+0xb2 0x78 0x0f 0xff
+
+#CHECK: stcke 4095(%r1)
+0xb2 0x78 0x1f 0xff
+
+#CHECK: stcke 4095(%r15)
+0xb2 0x78 0xff 0xff
+
+# CHECK: stfle 0
+0xb2 0xb0 0x00 0x00
+
+# CHECK: stfle 0(%r1)
+0xb2 0xb0 0x10 0x00
+
+#CHECK: stfle 0(%r15)
+0xb2 0xb0 0xf0 0x00
+
+#CHECK: stfle 4095
+0xb2 0xb0 0x0f 0xff
+
+#CHECK: stfle 4095(%r1)
+0xb2 0xb0 0x1f 0xff
+
+#CHECK: stfle 4095(%r15)
+0xb2 0xb0 0xff 0xff
+
+# CHECK: stcy %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0x72
# CHECK: stcy %r0, 0
Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=249015&r1=249014&r2=249015&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Thu Oct 1 09:43:48 2015
@@ -7946,6 +7946,62 @@
stc %r0, 4095(%r15,%r1)
stc %r15, 0
+#CHECK: stck 0 # encoding: [0xb2,0x05,0x00,0x00]
+#CHECK: stck 0(%r1) # encoding: [0xb2,0x05,0x10,0x00]
+#CHECK: stck 0(%r15) # encoding: [0xb2,0x05,0xf0,0x00]
+#CHECK: stck 4095 # encoding: [0xb2,0x05,0x0f,0xff]
+#CHECK: stck 4095(%r1) # encoding: [0xb2,0x05,0x1f,0xff]
+#CHECK: stck 4095(%r15) # encoding: [0xb2,0x05,0xff,0xff]
+
+ stck 0
+ stck 0(%r1)
+ stck 0(%r15)
+ stck 4095
+ stck 4095(%r1)
+ stck 4095(%r15)
+
+#CHECK: stckf 0 # encoding: [0xb2,0x7c,0x00,0x00]
+#CHECK: stckf 0(%r1) # encoding: [0xb2,0x7c,0x10,0x00]
+#CHECK: stckf 0(%r15) # encoding: [0xb2,0x7c,0xf0,0x00]
+#CHECK: stckf 4095 # encoding: [0xb2,0x7c,0x0f,0xff]
+#CHECK: stckf 4095(%r1) # encoding: [0xb2,0x7c,0x1f,0xff]
+#CHECK: stckf 4095(%r15) # encoding: [0xb2,0x7c,0xff,0xff]
+
+ stckf 0
+ stckf 0(%r1)
+ stckf 0(%r15)
+ stckf 4095
+ stckf 4095(%r1)
+ stckf 4095(%r15)
+
+#CHECK: stcke 0 # encoding: [0xb2,0x78,0x00,0x00]
+#CHECK: stcke 0(%r1) # encoding: [0xb2,0x78,0x10,0x00]
+#CHECK: stcke 0(%r15) # encoding: [0xb2,0x78,0xf0,0x00]
+#CHECK: stcke 4095 # encoding: [0xb2,0x78,0x0f,0xff]
+#CHECK: stcke 4095(%r1) # encoding: [0xb2,0x78,0x1f,0xff]
+#CHECK: stcke 4095(%r15) # encoding: [0xb2,0x78,0xff,0xff]
+
+ stcke 0
+ stcke 0(%r1)
+ stcke 0(%r15)
+ stcke 4095
+ stcke 4095(%r1)
+ stcke 4095(%r15)
+
+#CHECK: stfle 0 # encoding: [0xb2,0xb0,0x00,0x00]
+#CHECK: stfle 0(%r1) # encoding: [0xb2,0xb0,0x10,0x00]
+#CHECK: stfle 0(%r15) # encoding: [0xb2,0xb0,0xf0,0x00]
+#CHECK: stfle 4095 # encoding: [0xb2,0xb0,0x0f,0xff]
+#CHECK: stfle 4095(%r1) # encoding: [0xb2,0xb0,0x1f,0xff]
+#CHECK: stfle 4095(%r15) # encoding: [0xb2,0xb0,0xff,0xff]
+
+ stfle 0
+ stfle 0(%r1)
+ stfle 0(%r15)
+ stfle 4095
+ stfle 4095(%r1)
+ stfle 4095(%r15)
+
#CHECK: stcy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x72]
#CHECK: stcy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x72]
#CHECK: stcy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x72]
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