[PATCH] D13121: Improve ISel across lane float min/max reduction

[Jun Bum Lim via llvm-commits]

junbuml added inline comments.

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8601
@@ -8600,3 +8600,3 @@
   int NumVecElts = VTy.getVectorNumElements();
-  if (NumVecElts != 4 && NumVecElts != 8 && NumVecElts != 16)
-    return SDValue();
+  if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
+    if (NumVecElts != 4)
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jmolloy wrote:
> What about FMAXNAN and FMINNAN (-> FMAXV, FMINV)?
I also thought the same, but I wasn't able to generate FMAXNAN with a vector input. It appears that matchSelectPattern() cannot return SPNB_RETURNS_NAN with fcmp fast. And even without fast math flag, SPNB_RETURNS_NAN cannot be returned because both LHSSafe and RHSSafe in matchSelectPattern() are false for vector inputs. Please let me know if I miss something.
 
 

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8662
@@ -8656,3 +8661,3 @@
   case ISD::ADD:
-    Opcode = AArch64ISD::UADDV;
+    Opcode = Intrinsic::aarch64_neon_uaddv;
     break;
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jmolloy wrote:
> Why are you making this change? What's the rationale?
The only reason that I change to use intrinsics here is just to be consistent in the way I handle nodes because I could see only intrinsic of FMAXNMV, no SDNode for FMAXNMV. If SDNode need to be used I will add SDNode definition in td file for  FMAXNMV. Please let me know.
 


http://reviews.llvm.org/D13121