[PATCH] D13121: Improve ISel across lane float min/max reduction
James Molloy via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 20:04:05 PDT 2015
jmolloy added inline comments.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8601
@@ -8600,3 +8600,3 @@
int NumVecElts = VTy.getVectorNumElements();
- if (NumVecElts != 4 && NumVecElts != 8 && NumVecElts != 16)
- return SDValue();
+ if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) {
+ if (NumVecElts != 4)
----------------
What about FMAXNAN and FMINNAN (-> FMAXV, FMINV)?
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8662
@@ -8656,3 +8661,3 @@
case ISD::ADD:
- Opcode = AArch64ISD::UADDV;
+ Opcode = Intrinsic::aarch64_neon_uaddv;
break;
----------------
Why are you making this change? What's the rationale?
http://reviews.llvm.org/D13121
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