[PATCH] D11632: [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6

[Daniel Sanders via llvm-commits]

dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

LGTM with a few (mostly formatting) nits


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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp:796-797
@@ +795,4 @@
+getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
+                      SmallVectorImpl<MCFixup> &Fixups,
+                      const MCSubtargetInfo &STI) const {
+  // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
----------------
Indentation.

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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp:801
@@ +800,3 @@
+  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
+  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
+
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Space around operators

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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h:176-177
@@ -175,1 +175,4 @@
+  unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
----------------
Indentation

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Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:82
@@ -73,1 +81,3 @@
 
+class CACHEE_PREFE_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
+  bits<21> addr;
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Naming convention:  Should start with POOL32C_

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Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:168
@@ +167,3 @@
+class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
+                           RegisterOperand GPROpnd> : CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, GPROpnd> {
+  string DecoderMethod = "DecodePrefeOpMM";
----------------
Indentation


http://reviews.llvm.org/D11632