[PATCH] D12596: Fix for bootstrap bug introduced in r244921

[Nemanja Ivanovic via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: wschmidt, seurer, kbarton, hfinkel.
nemanjai added a subscriber: llvm-commits.
nemanjai set the repository for this revision to rL LLVM.

Since I have enabled building vectors using vector shuffles for v2i64 when direct moves are available, there was something I missed in PPCDAGToDAGISel::Select.
Namely, when a ISD::VECTOR_SHUFFLE is fed by an ISD::SCALAR_TO_VECTOR which is fed by an unindexed load, we were transforming the node to a VSX load and splat. However, since we produce an MTVSRD and a swap for ISD::SCALAR_TO_VECTOR, this is no longer the right thing to do.
So I have added logic to not change this scalar load to a VSX load-and-splat when we are building a v2i64 and have direct moves.

Repository:
  rL LLVM

http://reviews.llvm.org/D12596

Files:
  lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
  test/CodeGen/PowerPC/vsx.ll

Index: test/CodeGen/PowerPC/vsx.ll
===================================================================
--- test/CodeGen/PowerPC/vsx.ll
+++ test/CodeGen/PowerPC/vsx.ll
@@ -1226,14 +1226,14 @@
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test80
-; FIXME-CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3
-; FIXME-CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
-; FIXME-CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]]
-; FIXME-CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
-; FIXME-CHECK-LE-DAG: xxspltd 34, [[V1]]
-; FIXME-CHECK-LE-DAG: xxswapd 35, [[V2]]
-; FIXME-CHECK-LE: vaddudm 2, 2, 3
-; FIXME-CHECK-LE: blr
+; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3
+; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
+; CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]]
+; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
+; CHECK-LE-DAG: xxspltd 34, [[V1]]
+; CHECK-LE-DAG: xxswapd 35, [[V2]]
+; CHECK-LE: vaddudm 2, 2, 3
+; CHECK-LE: blr
 }
 
 define <2 x double> @test81(<4 x float> %b) {
Index: test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
===================================================================
--- test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -59,9 +59,9 @@
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
-; FIXME-CHECK: mtvsrd {{[0-9]+}}, 3
-; FIXME-CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
-; FIXME-CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
+; CHECK: mtvsrd {{[0-9]+}}, 3
+; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
+; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
 }
 
 ; Function Attrs: nounwind
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -550,8 +550,7 @@
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
-        // FIXME: this is causing bootstrap failures, disable temporarily
-        //setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
+        setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
       }
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
 
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -2780,9 +2780,17 @@
         else
           DM[i] = 1;
 
+      /* The SCALAR_TO_VECTOR of integers is handled by a direct move when
+         those are available. In that case, we can't just put in a VSX load
+         and splat here.
+      */
+      bool NotDirectMovable = !PPCSubTarget->hasDirectMove() ||
+                              N->getValueType(0) != MVT::v2i64;
+
       if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
           Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
-          isa<LoadSDNode>(Op1.getOperand(0))) {
+          isa<LoadSDNode>(Op1.getOperand(0)) &&
+          NotDirectMovable) {
         LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
         SDValue Base, Offset;
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D12596.33929.patch
Type: text/x-patch
Size: 3347 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150903/274b88a7/attachment.bin>