[PATCH] D12149: [AArch64] Turn on by default interleaved access vectorization

[silviu.baranga@arm.com via llvm-commits]

sbaranga added a comment.

In addition to Renato's reply:

In http://reviews.llvm.org/D12149#228259, @llvm-commits wrote:

> I’m not sure about this LG and have a number of questions:
>
> 1. Has the review of the actual interleave code been finished?
> 2. What is the compile-time impact?
> 3. Could you share detailed performance data on SPEC ref input (per benchmark) and perhaps some other suites you run on a regular basis?
> 4. Could count the number of times interleave vectorization per benchmark and see if there is a correlation to the run-time data you measure?


I'm taking a closer look at SPEC now, but I doubt there will be a strong correlation with run-time data (only if we get lucky and optimize a hot loop). The changes weren't significant either.

> 5. Do you expect impact on other architectures (not just ARM, ARM64 etc.). Data?


I suspect it wouldn't be beneficial unless the architectures backend has a way of efficiently lowering the load + shuffles to a reasonably fast instruction sequence (and this should also be reflected in the cost model). I had to do a number of fixes of fixes for ARM/AArch64 to remove the regressions I've found, so I wouldn't turn this on elsewhere without data.

> Thanks

> Gerolf


-Silviu


http://reviews.llvm.org/D12149