[PATCH] D12154: [x86] invert logic for attribute 'FeatureFastUAMem'

[Sanjay Patel via llvm-commits]

spatel added inline comments.

================
Comment at: lib/Target/X86/X86.td:489
@@ -486,1 +488,3 @@
+                               FeatureFSGSBase, FeatureSlowUAMem]>;
 
+def : Proc<"geode",           [FeatureSlowUAMem, Feature3DNowA]>;
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RKSimon wrote:
> You can drop FeatureSlowUAMem for BD targets - the AMD 15h SOG confirms that unaligned performance should be the same for aligned addresses and only +1cy for unaligned. It might be more complex for cache-line crossing but most targets will suffer there, not just BD.
Thanks, Simon. Can we make the same argument for AMD 16H? I was planning to fix these up in the next patch and add test cases since that would be a functional change (FIXME at line 445).


http://reviews.llvm.org/D12154