[PATCH] D12116: [AArch64] Improve load/store optimizer to handle LDUR + LDR.

[Kristof Beyls via llvm-commits]

kristof.beyls added inline comments.

================
Comment at: test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll:81
@@ +80,3 @@
+  ret i64 %add
+}
+
----------------
kristof.beyls wrote:
> Looking at this test case, I see that before this patch, the following code is produced:
>         ldur    x8, [x0, #-8]
>         ldr      x9, [x0]
> . If I'm not mistaken, ldur    x8, [x0, #-8] has the same functionality as ldr x8, [x0, #-1]? If so, wouldn't it be better to make sure
> we produce ldr instead of ldur in the first place?
> If we would do that, and there still is a good reason to have special code to convert LDR + LDUR into LDP, I guess none of the above test cases really show that (although I haven't investigated every single test case in detail)?
D'oh! The ARMARM clearly states that the scaled immediate offsets in ldr x8, [x0, #imm] can only be positive/unsigned. Please ignore my comment above!


Repository:
  rL LLVM

http://reviews.llvm.org/D12116