[PATCH] D12116: [AArch64] Improve load/store optimizer to handle LDUR + LDR.

[Kristof Beyls via llvm-commits]

kristof.beyls added inline comments.

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Comment at: test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll:1
@@ +1,2 @@
+; RUN: llc < %s -march=arm64 -aarch64-stp-suppress=false -verify-machineinstrs -mcpu=cortex-a57 | FileCheck %s
+
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My preference is to use -march=aarch64 instead of -march=arm64 as much as possible, as aarch64 is the official name for the architecture.
Is there a specific reason -mcpu=cortex-a57 needs to be added to the test line? I don't have a strong opinion on whether it should be there or not, just wondering.

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Comment at: test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll:81
@@ +80,3 @@
+  ret i64 %add
+}
+
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Looking at this test case, I see that before this patch, the following code is produced:
        ldur    x8, [x0, #-8]
        ldr      x9, [x0]
. If I'm not mistaken, ldur    x8, [x0, #-8] has the same functionality as ldr x8, [x0, #-1]? If so, wouldn't it be better to make sure
we produce ldr instead of ldur in the first place?
If we would do that, and there still is a good reason to have special code to convert LDR + LDUR into LDP, I guess none of the above test cases really show that (although I haven't investigated every single test case in detail)?


Repository:
  rL LLVM

http://reviews.llvm.org/D12116