[llvm] r244532 - Load/store for float registers from/to alternate space.

[James Y Knight via llvm-commits]

The FP load/store with ASI instructions aren't available in sparcv8, so
these additions need to be conditioned on HasV9.

On Mon, Aug 10, 2015 at 7:33 PM, Joerg Sonnenberger via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: joerg
> Date: Mon Aug 10 18:33:17 2015
> New Revision: 244532
>
> URL: http://llvm.org/viewvc/llvm-project?rev=244532&view=rev
> Log:
> Load/store for float registers from/to alternate space.
>
> Modified:
>     llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
>     llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=244532&r1=244531&r2=244532&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Mon Aug 10 18:33:17 2015
> @@ -413,11 +413,11 @@ let DecoderMethod = "DecodeLoadIntPair"
>
>  // Section B.2 - Load Floating-point Instructions, p. 92
>  let DecoderMethod = "DecodeLoadFP" in
> -  defm LDF   : Load<"ld",  0b100000, load, FPRegs,  f32>;
> +  defm LDF   : LoadA<"ld",  0b100000, 0b110000, load, FPRegs,  f32>;
>  let DecoderMethod = "DecodeLoadDFP" in
> -  defm LDDF  : Load<"ldd", 0b100011, load, DFPRegs, f64>;
> +  defm LDDF  : LoadA<"ldd", 0b100011, 0b110011, load, DFPRegs, f64>;
>  let DecoderMethod = "DecodeLoadQFP" in
> -  defm LDQF  : Load<"ldq", 0b100010, load, QFPRegs, f128>,
> +  defm LDQF  : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
>                 Requires<[HasV9, HasHardQuad]>;
>
>  // Section B.4 - Store Integer Instructions, p. 95
> @@ -432,11 +432,11 @@ let DecoderMethod = "DecodeStoreIntPair"
>
>  // Section B.5 - Store Floating-point Instructions, p. 97
>  let DecoderMethod = "DecodeStoreFP" in
> -  defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
> +  defm STF   : StoreA<"st",  0b100100, 0b110100, store,         FPRegs,
> f32>;
>  let DecoderMethod = "DecodeStoreDFP" in
> -  defm STDF  : Store<"std", 0b100111, store,         DFPRegs, f64>;
> +  defm STDF  : StoreA<"std", 0b100111, 0b110111, store,         DFPRegs,
> f64>;
>  let DecoderMethod = "DecodeStoreQFP" in
> -  defm STQF  : Store<"stq", 0b100110, store,         QFPRegs, f128>,
> +  defm STQF  : StoreA<"stq", 0b100110, 0b110110, store,         QFPRegs,
> f128>,
>                 Requires<[HasV9, HasHardQuad]>;
>
>  // Section B.8 - SWAP Register with Memory Instruction
>
> Modified: llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s?rev=244532&r1=244531&r2=244532&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s (original)
> +++ llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s Mon Aug 10 18:33:17
> 2015
> @@ -138,3 +138,32 @@
>          fdtox %f0, %f4
>          fqtox %f0, %f4
>
> +        ! CHECK: lda [%l0] 240, %f29             ! encoding:
> [0xfb,0x84,0x1e,0x00]
> +        ! CHECK: ld [%l0], %f29                  ! encoding:
> [0xfb,0x04,0x00,0x00]
> +        lda [%l0] 0xf0, %f29
> +        ld [%l0], %f29
> +
> +        ! CHECK: ldda [%l0] 240, %f48            ! encoding:
> [0xe3,0x9c,0x1e,0x00]
> +        ! CHECK: ldd [%l0], %f48                 ! encoding:
> [0xe3,0x1c,0x00,0x00]
> +        ldda [%l0] 0xf0, %f48
> +        ldd [%l0], %f48
> +
> +        ! CHECK: ldqa [%l0] 240, %f48            ! encoding:
> [0xe3,0x94,0x1e,0x00]
> +        ! CHECK: ldq [%l0], %f48                 ! encoding:
> [0xe3,0x14,0x00,0x00]
> +        ldqa [%l0] 0xf0, %f48
> +        ldq [%l0], %f48
> +
> +        ! CHECK: sta %f29, [%l0] 240             ! encoding:
> [0xfb,0xa4,0x1e,0x00]
> +        ! CHECK: st %f29, [%l0]                  ! encoding:
> [0xfb,0x24,0x00,0x00]
> +        sta %f29, [%l0] 0xf0
> +        st %f29, [%l0]
> +
> +        ! CHECK: stda %f48, [%l0] 240            ! encoding:
> [0xe3,0xbc,0x1e,0x00]
> +        ! CHECK: std %f48, [%l0]                 ! encoding:
> [0xe3,0x3c,0x00,0x00]
> +        stda %f48, [%l0] 0xf0
> +        std %f48, [%l0]
> +
> +        ! CHECK: stqa %f48, [%l0] 240            ! encoding:
> [0xe3,0xb4,0x1e,0x00]
> +        ! CHECK: stq %f48, [%l0]                 ! encoding:
> [0xe3,0x34,0x00,0x00]
> +        stqa %f48, [%l0] 0xf0
> +        stq %f48, [%l0]
>
>
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