<div dir="ltr">The FP load/store with ASI instructions aren't available in sparcv8, so these additions need to be conditioned on HasV9.</div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Aug 10, 2015 at 7:33 PM, Joerg Sonnenberger via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: joerg<br>
Date: Mon Aug 10 18:33:17 2015<br>
New Revision: 244532<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=244532&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=244532&view=rev</a><br>
Log:<br>
Load/store for float registers from/to alternate space.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td<br>
llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=244532&r1=244531&r2=244532&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=244532&r1=244531&r2=244532&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Mon Aug 10 18:33:17 2015<br>
@@ -413,11 +413,11 @@ let DecoderMethod = "DecodeLoadIntPair"<br>
<br>
// Section B.2 - Load Floating-point Instructions, p. 92<br>
let DecoderMethod = "DecodeLoadFP" in<br>
- defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;<br>
+ defm LDF : LoadA<"ld", 0b100000, 0b110000, load, FPRegs, f32>;<br>
let DecoderMethod = "DecodeLoadDFP" in<br>
- defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;<br>
+ defm LDDF : LoadA<"ldd", 0b100011, 0b110011, load, DFPRegs, f64>;<br>
let DecoderMethod = "DecodeLoadQFP" in<br>
- defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,<br>
+ defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,<br>
Requires<[HasV9, HasHardQuad]>;<br>
<br>
// Section B.4 - Store Integer Instructions, p. 95<br>
@@ -432,11 +432,11 @@ let DecoderMethod = "DecodeStoreIntPair"<br>
<br>
// Section B.5 - Store Floating-point Instructions, p. 97<br>
let DecoderMethod = "DecodeStoreFP" in<br>
- defm STF : Store<"st", 0b100100, store, FPRegs, f32>;<br>
+ defm STF : StoreA<"st", 0b100100, 0b110100, store, FPRegs, f32>;<br>
let DecoderMethod = "DecodeStoreDFP" in<br>
- defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;<br>
+ defm STDF : StoreA<"std", 0b100111, 0b110111, store, DFPRegs, f64>;<br>
let DecoderMethod = "DecodeStoreQFP" in<br>
- defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,<br>
+ defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,<br>
Requires<[HasV9, HasHardQuad]>;<br>
<br>
// Section B.8 - SWAP Register with Memory Instruction<br>
<br>
Modified: llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s?rev=244532&r1=244531&r2=244532&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s?rev=244532&r1=244531&r2=244532&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s (original)<br>
+++ llvm/trunk/test/MC/Sparc/sparc-fp-instructions.s Mon Aug 10 18:33:17 2015<br>
@@ -138,3 +138,32 @@<br>
fdtox %f0, %f4<br>
fqtox %f0, %f4<br>
<br>
+ ! CHECK: lda [%l0] 240, %f29 ! encoding: [0xfb,0x84,0x1e,0x00]<br>
+ ! CHECK: ld [%l0], %f29 ! encoding: [0xfb,0x04,0x00,0x00]<br>
+ lda [%l0] 0xf0, %f29<br>
+ ld [%l0], %f29<br>
+<br>
+ ! CHECK: ldda [%l0] 240, %f48 ! encoding: [0xe3,0x9c,0x1e,0x00]<br>
+ ! CHECK: ldd [%l0], %f48 ! encoding: [0xe3,0x1c,0x00,0x00]<br>
+ ldda [%l0] 0xf0, %f48<br>
+ ldd [%l0], %f48<br>
+<br>
+ ! CHECK: ldqa [%l0] 240, %f48 ! encoding: [0xe3,0x94,0x1e,0x00]<br>
+ ! CHECK: ldq [%l0], %f48 ! encoding: [0xe3,0x14,0x00,0x00]<br>
+ ldqa [%l0] 0xf0, %f48<br>
+ ldq [%l0], %f48<br>
+<br>
+ ! CHECK: sta %f29, [%l0] 240 ! encoding: [0xfb,0xa4,0x1e,0x00]<br>
+ ! CHECK: st %f29, [%l0] ! encoding: [0xfb,0x24,0x00,0x00]<br>
+ sta %f29, [%l0] 0xf0<br>
+ st %f29, [%l0]<br>
+<br>
+ ! CHECK: stda %f48, [%l0] 240 ! encoding: [0xe3,0xbc,0x1e,0x00]<br>
+ ! CHECK: std %f48, [%l0] ! encoding: [0xe3,0x3c,0x00,0x00]<br>
+ stda %f48, [%l0] 0xf0<br>
+ std %f48, [%l0]<br>
+<br>
+ ! CHECK: stqa %f48, [%l0] 240 ! encoding: [0xe3,0xb4,0x1e,0x00]<br>
+ ! CHECK: stq %f48, [%l0] ! encoding: [0xe3,0x34,0x00,0x00]<br>
+ stqa %f48, [%l0] 0xf0<br>
+ stq %f48, [%l0]<br>
<br>
<br>
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</blockquote></div><br></div>