[PATCH] D11428: Improve EmitLoweredSelect for contiguous pseudo CMOV instructions.

[Ahmed Bougacha]

ab added inline comments.

================
Comment at: test/CodeGen/X86/pseudo_cmov_lower.ll:219-224
@@ +218,8 @@
+; get lowered into vector length number of selects, which all eventually turn
+; into a huge number of CMOV_GR8, which are all contiguous, so the optimization
+; kicks in as long as CMOV_GR8 is supported. I couldn't find a way to get
+; CMOV_V*I1 pseudo-opcodes to get generated. If a way exists to get CMOV_V*1
+; pseudo-opcodes to be generated, this test should be replaced with one that
+; tests those opcodes.
+;
+; CHECK-LABEL: foo9:
----------------
Does enabling, say, avx512f work?


http://reviews.llvm.org/D11428