[PATCH] D11625: AMDGPU/SI: Set DwarfRegNum

[Matt Arsenault]

arsenm added inline comments.

================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:13-14
@@ -12,4 +12,4 @@
 //===----------------------------------------------------------------------===//
-
-class SIReg <string n, bits<16> encoding = 0> : Register<n> {
+class SIReg <string n, bits<16> regIdx = 0> : Register<n>,
+  DwarfRegNum<[!cast<int>(HWEncoding)]> {
   let Namespace = "AMDGPU";
----------------
tstellarAMD wrote:
> Is it OK for vgprs and sgprs to have the same DwarfRegNum?
I assume not. This isn't what's happening though. I originally was setting this from the encoding parameter to SIReg, but this was getting the same value for SGPRs and VGPRs, so I so I renamed it to regIdx and set it from HWEncoding because the VGPRs set HWEncoding{8} separately (although for the special registers regIdx isn't really an accurate name)


http://reviews.llvm.org/D11625