[llvm] r241927 - ComputeKnownBits: be a bit smarter about ADDs
Sean Silva
chisophugis at gmail.com
Fri Jul 10 20:58:05 PDT 2015
On Fri, Jul 10, 2015 at 11:29 AM, Fiona Glaser <escha at apple.com> wrote:
> Author: escha
> Date: Fri Jul 10 13:29:02 2015
> New Revision: 241927
>
> URL: http://llvm.org/viewvc/llvm-project?rev=241927&view=rev
> Log:
> ComputeKnownBits: be a bit smarter about ADDs
>
> If our two inputs have known top-zero bit counts M and N, we trivially
> know that the output cannot have any bits set in the top (min(M, N)-1)
> bits, since nothing could carry past that point.
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
> llvm/trunk/test/CodeGen/X86/win64_frame.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=241927&r1=241926&r2=241927&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jul 10
> 13:29:02 2015
> @@ -2356,15 +2356,24 @@ void SelectionDAG::computeKnownBits(SDVa
> // Output known-0 bits are known if clear or set in both the low
> clear bits
> // common to both LHS & RHS. For example, 8+(X<<3) is known to have
> the
> // low 3 bits clear.
> + // Output known-0 bits are also known if the top bits of each input
> are
> + // known to be clear. For example, if one input has the top 10 bits
> clear
> + // and the other has the top 8 bits clear, we know the top 7 bits of
> the
> + // output must be clear.
> computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
> - unsigned KnownZeroOut = KnownZero2.countTrailingOnes();
> + unsigned KnownZeroHigh = KnownZero2.countLeadingOnes();
> + unsigned KnownZeroLow = KnownZero2.countTrailingOnes();
>
> computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
> - KnownZeroOut = std::min(KnownZeroOut,
> + KnownZeroHigh = std::min(KnownZeroHigh,
> + KnownZero2.countLeadingOnes());
> + KnownZeroLow = std::min(KnownZeroLow,
> KnownZero2.countTrailingOnes());
>
> if (Op.getOpcode() == ISD::ADD) {
> - KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut);
> + KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow);
> + if (KnownZeroHigh > 1)
> + KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1);
> break;
> }
>
> @@ -2372,8 +2381,8 @@ void SelectionDAG::computeKnownBits(SDVa
> // information if we know (at least) that the low two bits are
> clear. We
> // then return to the caller that the low bit is unknown but that
> other bits
> // are known zero.
> - if (KnownZeroOut >= 2) // ADDE
> - KnownZero |= APInt::getBitsSet(BitWidth, 1, KnownZeroOut);
> + if (KnownZeroLow >= 2) // ADDE
> + KnownZero |= APInt::getBitsSet(BitWidth, 1, KnownZeroLow);
> break;
> }
> case ISD::SREM:
>
> Modified: llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll?rev=241927&r1=241926&r2=241927&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
> (original)
> +++ llvm/trunk/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll Fri
> Jul 10 13:29:02 2015
> @@ -255,7 +255,7 @@ entry:
> ; CHECK: ubfx x9, x0, #0, #32
> ; CHECK: lsl x9, x9, #2
> ; CHECK: add x9, x9, #15
> -; CHECK: and x9, x9, #0xfffffffffffffff0
> +; CHECK: and x9, x9, #0x7fffffff0
> ; CHECK: mov x10, sp
> ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
> ; CHECK: mov sp, x[[VLASPTMP]]
> @@ -302,7 +302,7 @@ entry:
> ; CHECK: ubfx x9, x0, #0, #32
> ; CHECK: lsl x9, x9, #2
> ; CHECK: add x9, x9, #15
> -; CHECK: and x9, x9, #0xfffffffffffffff0
> +; CHECK: and x9, x9, #0x7fffffff0
> ; CHECK: mov x10, sp
> ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
> ; CHECK: mov sp, x[[VLASPTMP]]
> @@ -364,7 +364,7 @@ entry:
> ; CHECK: ubfx x9, x0, #0, #32
> ; CHECK: lsl x9, x9, #2
> ; CHECK: add x9, x9, #15
> -; CHECK: and x9, x9, #0xfffffffffffffff0
> +; CHECK: and x9, x9, #0x7fffffff0
> ; CHECK: mov x10, sp
> ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
> ; CHECK: mov sp, x[[VLASPTMP]]
> @@ -417,7 +417,7 @@ entry:
> ; CHECK: ubfx x9, x0, #0, #32
> ; CHECK: lsl x9, x9, #2
> ; CHECK: add x9, x9, #15
> -; CHECK: and x9, x9, #0xfffffffffffffff0
> +; CHECK: and x9, x9, #0x7fffffff0
> ; CHECK: mov x10, sp
> ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
> ; CHECK: mov sp, x[[VLASPTMP]]
> @@ -468,7 +468,7 @@ entry:
> ; CHECK: ubfx x9, x0, #0, #32
> ; CHECK: lsl x9, x9, #2
> ; CHECK: add x9, x9, #15
> -; CHECK: and x9, x9, #0xfffffffffffffff0
> +; CHECK: and x9, x9, #0x7fffffff0
> ; CHECK: mov x10, sp
> ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
> ; CHECK: mov sp, x[[VLASPTMP]]
>
> Modified: llvm/trunk/test/CodeGen/X86/win64_frame.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_frame.ll?rev=241927&r1=241926&r2=241927&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/win64_frame.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/win64_frame.ll Fri Jul 10 13:29:02 2015
> @@ -100,8 +100,9 @@ define i32 @f8(i32 %a, i32 %b, i32 %c, i
>
> alloca i32, i32 %a
> ; CHECK: movl %ecx, %eax
> - ; CHECK: leaq 15(,%rax,4), %rax
> - ; CHECK: andq $-16, %rax
> + ; CHECK: leaq 15(,%rax,4), %rcx
> + ; CHECK: movabsq $34359738352, %rax
> + ; CHECK: andq %rcx, %rax
>
What's up with this giant immediate we're now generating instead of an
imm8? Seems worse.
-- Sean Silva
> ; CHECK: callq __chkstk
> ; CHECK: subq %rax, %rsp
>
>
>
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> llvm-commits at cs.uiuc.edu
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>
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