[llvm] r239806 - [AVX512] add integer min/max intrinsics support.
Ahmed Bougacha
ahmed.bougacha at gmail.com
Mon Jul 6 13:08:39 PDT 2015
On Mon, Jul 6, 2015 at 9:52 PM, Quentin Colombet <qcolombet at apple.com>
wrote:
>
> On Jul 4, 2015, at 11:53 PM, Demikhovsky, Elena <
> elena.demikhovsky at intel.com> wrote:
>
> > If you'll always want to use the avx512 encoding it seems a little
> wasteful
> Yes, you are right. But we choose AVX-512 form on instruction selection
> phase, it gives more registers - 32 instead of 16.
> We are adding “NoVLX” , “UseAVX” and other predicates to AVX patterns to
> switch them off in KNL/SKX modes.
>
> We’ll need to add a pass after register allocation and replace the long
> AVX-512 encoding with AVX encoding when possible, but we are not there yet.
>
>
> IIRC, ARM does something similar for thumb. Making we can factorize this
> pass into something generic with hooks?
>
Yes, there's also the (simpler) A-register specific encodings on X86 (done
during MCInst lowering IIRC; I don't know how ARM does it).
Also, this is https://llvm.org/bugs/show_bug.cgi?id=23376
-Ahmed
> My 2c.
>
> Cheers,
> Q
>
>
>
> - * Elena*
>
> *From:* Eric Christopher [mailto:echristo at gmail.com <echristo at gmail.com>]
> *Sent:* Saturday, July 04, 2015 22:10
> *To:* Badouh, Asaf; llvm-commits at cs.uiuc.edu; Demikhovsky, Elena
> *Subject:* Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics
> support.
>
>
>
> On Thu, Jul 2, 2015 at 7:04 AM Badouh, Asaf <asaf.badouh at intel.com> wrote:
>
> The registers are not always zmm, they might be xmm/ymm as well.
> Same for the K masks, not always exists.
> That’s why we thought the best way is to check the prefix.
>
> Sure, but let's say you're implementing an assembler, how do you know
> which encoding to use if you get one using xmm/ymm and no k mask?
>
> If you'll always want to use the avx512 encoding it seems a little
> wasteful, but you could also verify that you're assembling correctly via an
> MC test. If you'll want to base it upon the existence of the register or a
> k mask then you can do that by checking the assembly and not the encoding.
>
> I could be missing something though? :)
>
> -eric
>
>
> -Asaf
>
> *From:* Eric Christopher [mailto:echristo at gmail.com]
> *Sent:* Thursday, July 02, 2015 00:56
>
> *To:* Badouh, Asaf; llvm-commits at cs.uiuc.edu; Demikhovsky, Elena
> *Subject:* Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics
> support.
>
>
>
> On Sun, Jun 21, 2015 at 4:28 AM Badouh, Asaf <asaf.badouh at intel.com>
> wrote:
>
> Hey Eric,
> That part of the test is not new, it just moved from other part of the
> file.
> Anyway (ElenaD & I) agree, it will be better to keep the encoding part out
> of these tests.
> But we think we should keep the prefix of the encoding to make sure it’s
> generate AVX512 code. E.g:
> + ; CHECK: vpmaxsq {{.*}}encoding: [0x62
> is that ok with you?
>
>
> Can't you just check the register here or whether or not the k mask
> exists? (I mean, for this instruction in particular it's always going to be
> avx512 so not an issue, but the general idea applies).
>
> I guess if it's not deducible otherwise, sure, but I find it hard to
> believe it's completely unknowable from text.
>
> -eric
>
>
> -Asaf
>
> *From:* Eric Christopher [mailto:echristo at gmail.com]
> *Sent:* Friday, June 19, 2015 03:55
> *To:* Badouh, Asaf; llvm-commits at cs.uiuc.edu; Demikhovsky, Elena
> *Subject:* Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics
> support.
>
> Hi Asaf,
>
> I have a question here:
>
>
>
> +
> +define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {
> + ; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]
>
>
> Why are you checking the encoding of instructions in the CodeGen tests?
> This sort of thing belongs in the MC tests for the instructions. It looks
> like there are already encoding tests so I'm not sure what you're
> attempting to check here? You don't appear to be checking the actual
> operands to the instruction.
>
> -eric
>
>
>
> + %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0,
> <8 x i64> %a1,
> + <8 x i64>zeroinitializer, i8 -1)
> + ret <8 x i64> %res
> +}
> +declare <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64>, <8 x i64>,
> <8 x i64>, i8)
> +
> +define <16 x i32> @test_vpminud(<16 x i32> %a0, <16 x i32> %a1) {
> + ; CHECK: vpminud {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3b,0xc1]
> + %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>
> %a0, <16 x i32> %a1,
> + <16 x i32>zeroinitializer, i16 -1)
> + ret <16 x i32> %res
> +}
> +declare <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>, <16 x
> i32>, <16 x i32>, i16)
> +
> +define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {
> + ; CHECK: vpmaxsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3d,0xc1]
> + %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>
> %a0, <16 x i32> %a1,
> + <16 x i32>zeroinitializer, i16 -1)
> + ret <16 x i32> %res
> +}
> +declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x
> i32>, <16 x i32>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxsd %zmm
> +; CHECK: {%k1}
> +define <16 x i32>@test_int_x86_avx512_mask_pmaxs_d_512(<16 x i32> %x0,
> <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
> + %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
> + %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
> + %res2 = add <16 x i32> %res, %res1
> + ret <16 x i32> %res2
> +}
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxsq %zmm
> +; CHECK: {%k1}
> +define <8 x i64>@test_int_x86_avx512_mask_pmaxs_q_512(<8 x i64> %x0, <8 x
> i64> %x1, <8 x i64> %x2, i8 %x3) {
> + %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
> + %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 -1)
> + %res2 = add <8 x i64> %res, %res1
> + ret <8 x i64> %res2
> +}
> +
> +declare <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32>, <16 x
> i32>, <16 x i32>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxud %zmm
> +; CHECK: {%k1}
> +define <16 x i32>@test_int_x86_avx512_mask_pmaxu_d_512(<16 x i32> %x0,
> <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
> + %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
> + %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
> + %res2 = add <16 x i32> %res, %res1
> + ret <16 x i32> %res2
> +}
> +
> +declare <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64>, <8 x i64>,
> <8 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxuq %zmm
> +; CHECK: {%k1}
> +define <8 x i64>@test_int_x86_avx512_mask_pmaxu_q_512(<8 x i64> %x0, <8 x
> i64> %x1, <8 x i64> %x2, i8 %x3) {
> + %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
> + %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 -1)
> + %res2 = add <8 x i64> %res, %res1
> + ret <8 x i64> %res2
> +}
> +
> +declare <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32>, <16 x
> i32>, <16 x i32>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_512
> +; CHECK-NOT: call
> +; CHECK: vpminsd %zmm
> +; CHECK: {%k1}
> +define <16 x i32>@test_int_x86_avx512_mask_pmins_d_512(<16 x i32> %x0,
> <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
> + %res = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
> + %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
> + %res2 = add <16 x i32> %res, %res1
> + ret <16 x i32> %res2
> +}
> +
> +declare <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64>, <8 x i64>,
> <8 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_512
> +; CHECK-NOT: call
> +; CHECK: vpminsq %zmm
> +; CHECK: {%k1}
> +define <8 x i64>@test_int_x86_avx512_mask_pmins_q_512(<8 x i64> %x0, <8 x
> i64> %x1, <8 x i64> %x2, i8 %x3) {
> + %res = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
> + %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 -1)
> + %res2 = add <8 x i64> %res, %res1
> + ret <8 x i64> %res2
> +}
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_512
> +; CHECK-NOT: call
> +; CHECK: vpminud %zmm
> +; CHECK: {%k1}
> +define <16 x i32>@test_int_x86_avx512_mask_pminu_d_512(<16 x i32> %x0,
> <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {
> + %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)
> + %res1 = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>
> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)
> + %res2 = add <16 x i32> %res, %res1
> + ret <16 x i32> %res2
> +}
> +
> +declare <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64>, <8 x i64>,
> <8 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_512
> +; CHECK-NOT: call
> +; CHECK: vpminuq %zmm
> +; CHECK: {%k1}
> +define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x
> i64> %x1, <8 x i64> %x2, i8 %x3) {
> + %res = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 %x3)
> + %res1 = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0,
> <8 x i64> %x1, <8 x i64> %x2, i8 -1)
> + %res2 = add <8 x i64> %res, %res1
> + ret <8 x i64> %res2
> +}
>
> Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff
> <https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bw-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=l2CfvWbH5zN6oCcS_BQGHT9gvjP9HJeuucNqMArPh6E&e=>
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll Tue Jun 16 03:39:27
> 2015
> @@ -788,3 +788,107 @@ define <32 x i16> @test_mask_subs_epu16_
> }
>
> declare <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16>, <32 x
> i16>, <32 x i16>, i32)
> +
> +declare <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8>, <64 x i8>,
> <64 x i8>, i64)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxsb %zmm
> +; CHECK: {%k1}
> +define <64 x i8>@test_int_x86_avx512_mask_pmaxs_b_512(<64 x i8> %x0, <64
> x i8> %x1, <64 x i8> %x2, i64 %x3) {
> + %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 %x3)
> + %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 -1)
> + %res2 = add <64 x i8> %res, %res1
> + ret <64 x i8> %res2
> +}
> +
> +declare <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16>, <32 x
> i16>, <32 x i16>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxsw %zmm
> +; CHECK: {%k1}
> +define <32 x i16>@test_int_x86_avx512_mask_pmaxs_w_512(<32 x i16> %x0,
> <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
> + %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
> + %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
> + %res2 = add <32 x i16> %res, %res1
> + ret <32 x i16> %res2
> +}
> +
> +declare <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8>, <64 x i8>,
> <64 x i8>, i64)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxub %zmm
> +; CHECK: {%k1}
> +define <64 x i8>@test_int_x86_avx512_mask_pmaxu_b_512(<64 x i8> %x0, <64
> x i8> %x1, <64 x i8> %x2, i64 %x3) {
> + %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 %x3)
> + %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 -1)
> + %res2 = add <64 x i8> %res, %res1
> + ret <64 x i8> %res2
> +}
> +
> +declare <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16>, <32 x
> i16>, <32 x i16>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_512
> +; CHECK-NOT: call
> +; CHECK: vpmaxuw %zmm
> +; CHECK: {%k1}
> +define <32 x i16>@test_int_x86_avx512_mask_pmaxu_w_512(<32 x i16> %x0,
> <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
> + %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
> + %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
> + %res2 = add <32 x i16> %res, %res1
> + ret <32 x i16> %res2
> +}
> +
> +declare <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8>, <64 x i8>,
> <64 x i8>, i64)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_512
> +; CHECK-NOT: call
> +; CHECK: vpminsb %zmm
> +; CHECK: {%k1}
> +define <64 x i8>@test_int_x86_avx512_mask_pmins_b_512(<64 x i8> %x0, <64
> x i8> %x1, <64 x i8> %x2, i64 %x3) {
> + %res = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 %x3)
> + %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 -1)
> + %res2 = add <64 x i8> %res, %res1
> + ret <64 x i8> %res2
> +}
> +
> +declare <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16>, <32 x
> i16>, <32 x i16>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_512
> +; CHECK-NOT: call
> +; CHECK: vpminsw %zmm
> +; CHECK: {%k1}
> +define <32 x i16>@test_int_x86_avx512_mask_pmins_w_512(<32 x i16> %x0,
> <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
> + %res = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
> + %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
> + %res2 = add <32 x i16> %res, %res1
> + ret <32 x i16> %res2
> +}
> +
> +declare <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8>, <64 x i8>,
> <64 x i8>, i64)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_512
> +; CHECK-NOT: call
> +; CHECK: vpminub %zmm
> +; CHECK: {%k1}
> +define <64 x i8>@test_int_x86_avx512_mask_pminu_b_512(<64 x i8> %x0, <64
> x i8> %x1, <64 x i8> %x2, i64 %x3) {
> + %res = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 %x3)
> + %res1 = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0,
> <64 x i8> %x1, <64 x i8> %x2, i64 -1)
> + %res2 = add <64 x i8> %res, %res1
> + ret <64 x i8> %res2
> +}
> +
> +declare <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16>, <32 x
> i16>, <32 x i16>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_512
> +; CHECK-NOT: call
> +; CHECK: vpminuw %zmm
> +; CHECK: {%k1}
> +define <32 x i16>@test_int_x86_avx512_mask_pminu_w_512(<32 x i16> %x0,
> <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
> + %res = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)
> + %res1 = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16>
> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)
> + %res2 = add <32 x i16> %res, %res1
> + ret <32 x i16> %res2
> +}
>
> Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff
> <https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bwvl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=MtmaJB0CzZzn3oacEiXC67zfqRtscKdLRstzKzdNyIk&e=>
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll Tue Jun 16
> 03:39:27 2015
> @@ -2667,4 +2667,212 @@ define <32 x i8> @test_mask_subs_epu8_rm
> ret <32 x i8> %res
> }
>
> -declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x
> i8>, <32 x i8>, i32)
> \ No newline at end of file
> +declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x
> i8>, <32 x i8>, i32)
> +
> +declare <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8>, <16 x i8>,
> <16 x i8>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxsb %xmm
> +; CHECK: {%k1}
> +define <16 x i8>@test_int_x86_avx512_mask_pmaxs_b_128(<16 x i8> %x0, <16
> x i8> %x1, <16 x i8> %x2, i16 %mask) {
> + %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> %x2 ,i16 %mask)
> + %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i8> %res, %res1
> + ret <16 x i8> %res2
> +}
> +
> +declare <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8>, <32 x i8>,
> <32 x i8>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxsb %ymm
> +; CHECK: {%k1}
> +define <32 x i8>@test_int_x86_avx512_mask_pmaxs_b_256(<32 x i8> %x0, <32
> x i8> %x1, <32 x i8> %x2, i32 %x3) {
> + %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
> + %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 -1)
> + %res2 = add <32 x i8> %res, %res1
> + ret <32 x i8> %res2
> +}
> +
> +declare <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16>, <8 x i16>,
> <8 x i16>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxsw %xmm
> +; CHECK: {%k1}
> +define <8 x i16>@test_int_x86_avx512_mask_pmaxs_w_128(<8 x i16> %x0, <8 x
> i16> %x1, <8 x i16> %x2, i8 %x3) {
> + %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
> + %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 -1)
> + %res2 = add <8 x i16> %res, %res1
> + ret <8 x i16> %res2
> +}
> +
> +declare <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16>, <16 x
> i16>, <16 x i16>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxsw %ymm
> +; CHECK: {%k1}
> +define <16 x i16>@test_int_x86_avx512_mask_pmaxs_w_256(<16 x i16> %x0,
> <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {
> + %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)
> + %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i16> %res, %res1
> + ret <16 x i16> %res2
> +}
> +
> +declare <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8>, <16 x i8>,
> <16 x i8>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxub %xmm
> +; CHECK: {%k1}
> +define <16 x i8>@test_int_x86_avx512_mask_pmaxu_b_128(<16 x i8> %x0, <16
> x i8> %x1, <16 x i8> %x2,i16 %mask) {
> + %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> %x2, i16 %mask)
> + %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i8> %res, %res1
> + ret <16 x i8> %res2
> +}
> +
> +declare <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8>, <32 x i8>,
> <32 x i8>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxub %ymm
> +; CHECK: {%k1}
> +define <32 x i8>@test_int_x86_avx512_mask_pmaxu_b_256(<32 x i8> %x0, <32
> x i8> %x1, <32 x i8> %x2, i32 %x3) {
> + %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
> + %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 -1)
> + %res2 = add <32 x i8> %res, %res1
> + ret <32 x i8> %res2
> +}
> +
> +declare <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16>, <8 x i16>,
> <8 x i16>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxuw %xmm
> +; CHECK: {%k1}
> +define <8 x i16>@test_int_x86_avx512_mask_pmaxu_w_128(<8 x i16> %x0, <8 x
> i16> %x1, <8 x i16> %x2, i8 %x3) {
> + %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
> + %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 -1)
> + %res2 = add <8 x i16> %res, %res1
> + ret <8 x i16> %res2
> +}
> +
> +declare <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16>, <16 x
> i16>, <16 x i16>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxuw %ymm
> +; CHECK: {%k1}
> +define <16 x i16>@test_int_x86_avx512_mask_pmaxu_w_256(<16 x i16> %x0,
> <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {
> + %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)
> + %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i16> %res, %res1
> + ret <16 x i16> %res2
> +}
> +
> +declare <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8>, <16 x i8>,
> <16 x i8>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_128
> +; CHECK-NOT: call
> +; CHECK: vpminsb %xmm
> +; CHECK: {%k1}
> +define <16 x i8>@test_int_x86_avx512_mask_pmins_b_128(<16 x i8> %x0, <16
> x i8> %x1, <16 x i8> %x2, i16 %mask) {
> + %res = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> %x2, i16 %mask)
> + %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i8> %res, %res1
> + ret <16 x i8> %res2
> +}
> +
> +declare <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8>, <32 x i8>,
> <32 x i8>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_256
> +; CHECK-NOT: call
> +; CHECK: vpminsb %ymm
> +; CHECK: {%k1}
> +define <32 x i8>@test_int_x86_avx512_mask_pmins_b_256(<32 x i8> %x0, <32
> x i8> %x1, <32 x i8> %x2, i32 %x3) {
> + %res = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
> + %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 -1)
> + %res2 = add <32 x i8> %res, %res1
> + ret <32 x i8> %res2
> +}
> +
> +declare <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16>, <8 x i16>,
> <8 x i16>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_128
> +; CHECK-NOT: call
> +; CHECK: vpminsw %xmm
> +; CHECK: {%k1}
> +define <8 x i16>@test_int_x86_avx512_mask_pmins_w_128(<8 x i16> %x0, <8 x
> i16> %x1, <8 x i16> %x2, i8 %x3) {
> + %res = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
> + %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 -1)
> + %res2 = add <8 x i16> %res, %res1
> + ret <8 x i16> %res2
> +}
> +
> +declare <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16>, <16 x
> i16>, <16 x i16>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_256
> +; CHECK-NOT: call
> +; CHECK: vpminsw %ymm
> +; CHECK: {%k1}
> +define <16 x i16>@test_int_x86_avx512_mask_pmins_w_256(<16 x i16> %x0,
> <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {
> + %res = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)
> + %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i16> %res, %res1
> + ret <16 x i16> %res2
> +}
> +
> +declare <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8>, <16 x i8>,
> <16 x i8>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_128
> +; CHECK-NOT: call
> +; CHECK: vpminub %xmm
> +; CHECK: {%k1}
> +define <16 x i8>@test_int_x86_avx512_mask_pminu_b_128(<16 x i8> %x0, <16
> x i8> %x1, <16 x i8> %x2, i16 %mask) {
> + %res = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> %x2, i16 %mask)
> + %res1 = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0,
> <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i8> %res, %res1
> + ret <16 x i8> %res2
> +}
> +
> +declare <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8>, <32 x i8>,
> <32 x i8>, i32)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_256
> +; CHECK-NOT: call
> +; CHECK: vpminub %ymm
> +; CHECK: {%k1}
> +define <32 x i8>@test_int_x86_avx512_mask_pminu_b_256(<32 x i8> %x0, <32
> x i8> %x1, <32 x i8> %x2, i32 %x3) {
> + %res = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
> + %res1 = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0,
> <32 x i8> %x1, <32 x i8> %x2, i32 -1)
> + %res2 = add <32 x i8> %res, %res1
> + ret <32 x i8> %res2
> +}
> +
> +declare <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16>, <8 x i16>,
> <8 x i16>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_128
> +; CHECK-NOT: call
> +; CHECK: vpminuw %xmm
> +; CHECK: {%k1}
> +define <8 x i16>@test_int_x86_avx512_mask_pminu_w_128(<8 x i16> %x0, <8 x
> i16> %x1, <8 x i16> %x2, i8 %x3) {
> + %res = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 %x3)
> + %res1 = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0,
> <8 x i16> %x1, <8 x i16> %x2, i8 -1)
> + %res2 = add <8 x i16> %res, %res1
> + ret <8 x i16> %res2
> +}
> +
> +declare <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16>, <16 x
> i16>, <16 x i16>, i16)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_256
> +; CHECK-NOT: call
> +; CHECK: vpminuw %ymm
> +; CHECK: {%k1}
> +define <16 x i16>@test_int_x86_avx512_mask_pminu_w_256(<16 x i16> %x0,
> <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {
> + %res = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)
> + %res1 = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16>
> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)
> + %res2 = add <16 x i16> %res, %res1
> + ret <16 x i16> %res2
> +}
>
> Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff
> <https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512vl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=zwhhFLV2ynU3ASlzxB54u4fXW6WuknAXsqatLJz0MFs&e=>
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Tue Jun 16 03:39:27
> 2015
> @@ -2586,4 +2586,212 @@ define <8 x float> @test_getexp_ps_256(<
> %res = call <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>
> %a0, <8 x float> zeroinitializer, i8 -1)
> ret <8 x float> %res
> }
> -declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x
> float>, i8) nounwind readnone
> \ No newline at end of file
> +declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x
> float>, i8) nounwind readnone
> +
> +declare <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32>, <4 x i32>,
> <4 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxsd %xmm
> +; CHECK: {%k1}
> +define <4 x i32>@test_int_x86_avx512_mask_pmaxs_d_128(<4 x i32> %x0, <4 x
> i32> %x1, <4 x i32> %x2, i8 %mask) {
> + %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> %x2 ,i8 %mask)
> + %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i32> %res, %res1
> + ret <4 x i32> %res2
> +}
> +
> +declare <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32>, <8 x i32>,
> <8 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxsd %ymm
> +; CHECK: {%k1}
> +define <8 x i32>@test_int_x86_avx512_mask_pmaxs_d_256(<8 x i32> %x0, <8 x
> i32> %x1, <8 x i32> %x2, i8 %x3) {
> + %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
> + %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 -1)
> + %res2 = add <8 x i32> %res, %res1
> + ret <8 x i32> %res2
> +}
> +
> +declare <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64>, <2 x i64>,
> <2 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxsq %xmm
> +; CHECK: {%k1}
> +define <2 x i64>@test_int_x86_avx512_mask_pmaxs_q_128(<2 x i64> %x0, <2 x
> i64> %x1, <2 x i64> %x2, i8 %x3) {
> + %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
> + %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 -1)
> + %res2 = add <2 x i64> %res, %res1
> + ret <2 x i64> %res2
> +}
> +
> +declare <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64>, <4 x i64>,
> <4 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxsq %ymm
> +; CHECK: {%k1}
> +define <4 x i64>@test_int_x86_avx512_mask_pmaxs_q_256(<4 x i64> %x0, <4 x
> i64> %x1, <4 x i64> %x2, i8 %mask) {
> + %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> %x2, i8 %mask)
> + %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i64> %res, %res1
> + ret <4 x i64> %res2
> +}
> +
> +declare <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32>, <4 x i32>,
> <4 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxud %xmm
> +; CHECK: {%k1}
> +define <4 x i32>@test_int_x86_avx512_mask_pmaxu_d_128(<4 x i32> %x0, <4 x
> i32> %x1, <4 x i32> %x2,i8 %mask) {
> + %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> %x2, i8 %mask)
> + %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i32> %res, %res1
> + ret <4 x i32> %res2
> +}
> +
> +declare <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32>, <8 x i32>,
> <8 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxud %ymm
> +; CHECK: {%k1}
> +define <8 x i32>@test_int_x86_avx512_mask_pmaxu_d_256(<8 x i32> %x0, <8 x
> i32> %x1, <8 x i32> %x2, i8 %x3) {
> + %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
> + %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 -1)
> + %res2 = add <8 x i32> %res, %res1
> + ret <8 x i32> %res2
> +}
> +
> +declare <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64>, <2 x i64>,
> <2 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_128
> +; CHECK-NOT: call
> +; CHECK: vpmaxuq %xmm
> +; CHECK: {%k1}
> +define <2 x i64>@test_int_x86_avx512_mask_pmaxu_q_128(<2 x i64> %x0, <2 x
> i64> %x1, <2 x i64> %x2, i8 %x3) {
> + %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
> + %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 -1)
> + %res2 = add <2 x i64> %res, %res1
> + ret <2 x i64> %res2
> +}
> +
> +declare <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64>, <4 x i64>,
> <4 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_256
> +; CHECK-NOT: call
> +; CHECK: vpmaxuq %ymm
> +; CHECK: {%k1}
> +define <4 x i64>@test_int_x86_avx512_mask_pmaxu_q_256(<4 x i64> %x0, <4 x
> i64> %x1, <4 x i64> %x2, i8 %mask) {
> + %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> %x2, i8 %mask)
> + %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i64> %res, %res1
> + ret <4 x i64> %res2
> +}
> +
> +declare <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32>, <4 x i32>,
> <4 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_128
> +; CHECK-NOT: call
> +; CHECK: vpminsd %xmm
> +; CHECK: {%k1}
> +define <4 x i32>@test_int_x86_avx512_mask_pmins_d_128(<4 x i32> %x0, <4 x
> i32> %x1, <4 x i32> %x2, i8 %mask) {
> + %res = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> %x2, i8 %mask)
> + %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i32> %res, %res1
> + ret <4 x i32> %res2
> +}
> +
> +declare <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32>, <8 x i32>,
> <8 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_256
> +; CHECK-NOT: call
> +; CHECK: vpminsd %ymm
> +; CHECK: {%k1}
> +define <8 x i32>@test_int_x86_avx512_mask_pmins_d_256(<8 x i32> %x0, <8 x
> i32> %x1, <8 x i32> %x2, i8 %x3) {
> + %res = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
> + %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 -1)
> + %res2 = add <8 x i32> %res, %res1
> + ret <8 x i32> %res2
> +}
> +
> +declare <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64>, <2 x i64>,
> <2 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_128
> +; CHECK-NOT: call
> +; CHECK: vpminsq %xmm
> +; CHECK: {%k1}
> +define <2 x i64>@test_int_x86_avx512_mask_pmins_q_128(<2 x i64> %x0, <2 x
> i64> %x1, <2 x i64> %x2, i8 %x3) {
> + %res = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
> + %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 -1)
> + %res2 = add <2 x i64> %res, %res1
> + ret <2 x i64> %res2
> +}
> +
> +declare <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64>, <4 x i64>,
> <4 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_256
> +; CHECK-NOT: call
> +; CHECK: vpminsq %ymm
> +; CHECK: {%k1}
> +define <4 x i64>@test_int_x86_avx512_mask_pmins_q_256(<4 x i64> %x0, <4 x
> i64> %x1, <4 x i64> %x2, i8 %mask) {
> + %res = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> %x2, i8 %mask)
> + %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i64> %res, %res1
> + ret <4 x i64> %res2
> +}
> +
> +declare <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32>, <4 x i32>,
> <4 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_128
> +; CHECK-NOT: call
> +; CHECK: vpminud %xmm
> +; CHECK: {%k1}
> +define <4 x i32>@test_int_x86_avx512_mask_pminu_d_128(<4 x i32> %x0, <4 x
> i32> %x1, <4 x i32> %x2, i8 %mask) {
> + %res = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> %x2, i8 %mask)
> + %res1 = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0,
> <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i32> %res, %res1
> + ret <4 x i32> %res2
> +}
> +
> +declare <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32>, <8 x i32>,
> <8 x i32>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_256
> +; CHECK-NOT: call
> +; CHECK: vpminud %ymm
> +; CHECK: {%k1}
> +define <8 x i32>@test_int_x86_avx512_mask_pminu_d_256(<8 x i32> %x0, <8 x
> i32> %x1, <8 x i32> %x2, i8 %x3) {
> + %res = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 %x3)
> + %res1 = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0,
> <8 x i32> %x1, <8 x i32> %x2, i8 -1)
> + %res2 = add <8 x i32> %res, %res1
> + ret <8 x i32> %res2
> +}
> +
> +declare <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64>, <2 x i64>,
> <2 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_128
> +; CHECK-NOT: call
> +; CHECK: vpminuq %xmm
> +; CHECK: {%k1}
> +define <2 x i64>@test_int_x86_avx512_mask_pminu_q_128(<2 x i64> %x0, <2 x
> i64> %x1, <2 x i64> %x2, i8 %x3) {
> + %res = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 %x3)
> + %res1 = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0,
> <2 x i64> %x1, <2 x i64> %x2, i8 -1)
> + %res2 = add <2 x i64> %res, %res1
> + ret <2 x i64> %res2
> +}
> +
> +declare <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64>, <4 x i64>,
> <4 x i64>, i8)
> +
> +; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_256
> +; CHECK-NOT: call
> +; CHECK: vpminuq %ymm
> +; CHECK: {%k1}
> +define <4 x i64>@test_int_x86_avx512_mask_pminu_q_256(<4 x i64> %x0, <4 x
> i64> %x1, <4 x i64> %x2, i8 %mask) {
> + %res = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> %x2, i8 %mask)
> + %res1 = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0,
> <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)
> + %res2 = add <4 x i64> %res, %res1
> + ret <4 x i64> %res2
> +}
> \ No newline at end of file
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
>
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.
>
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
>
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.
>
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
>
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150706/0a357659/attachment.html>
More information about the llvm-commits
mailing list