<div dir="ltr"><span style="line-height:normal">On Mon, Jul 6, 2015 at 9:52 PM, Quentin Colombet </span><span dir="ltr" style="line-height:normal"><<a href="mailto:qcolombet@apple.com" target="_blank">qcolombet@apple.com</a>></span><span style="line-height:normal"> wrote:</span><br><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div style="word-wrap:break-word"><br><div><span class=""><blockquote type="cite"><div>On Jul 4, 2015, at 11:53 PM, Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>> wrote:</div><br><div><div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px"><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">><span> </span></span>If you'll always want to use the avx512 encoding it seems a little wasteful<u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">Yes, you are right. But we choose AVX-512 form on instruction selection phase, it gives more registers - 32 instead of 16.<u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">We are adding “NoVLX” , “UseAVX” and other predicates to AVX patterns to switch them off in KNL/SKX modes.<u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><u></u> <u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">We’ll need to add a pass after register allocation and replace the long AVX-512 encoding with AVX encoding when possible, but we are not there yet.</div></div></div></blockquote><div><br></div></span><div>IIRC, ARM does something similar for thumb. Making we can factorize this pass into something generic with hooks?</div></div></div></blockquote><div><br></div><div>Yes, there's also the (simpler) A-register specific encodings on X86 (done during MCInst lowering IIRC; I don't know how ARM does it).</div><div>Also, this is <a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__llvm.org_bugs_show-5Fbug.cgi-3Fid-3D23376&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=7X6z_od7kyMgvpJ35q4usNUUhvCFc5pCTscVJQ-3X0Y&s=N64Sd6Qx9IkJTz_3AUp8Ayy-KNDZrwqcbVOPspyLJf0&e=">https://llvm.org/bugs/show_bug.cgi?id=23376</a></div><div><br></div><div>-Ahmed</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div style="word-wrap:break-word"><div><div>My 2c.</div><div><br></div><div>Cheers,</div><div><div class="h5"><div>Q</div><br><blockquote type="cite"><div><div style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px"><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"> </span></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"> </span></div><div style="margin:0cm 0cm 0.0001pt 36pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-family:Calibri,sans-serif;color:rgb(49,132,155)"><span>-<span style="font-style:normal;font-variant:normal;font-weight:normal;font-size:7pt;line-height:normal;font-family:'Times New Roman'"> <span> </span></span></span></span><span dir="LTR"></span><b><i><span style="color:rgb(49,132,155)"> Elena<u></u><u></u></span></i></b></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"> </span></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><b><span style="font-size:10pt;font-family:Tahoma,sans-serif">From:</span></b><span style="font-size:10pt;font-family:Tahoma,sans-serif"><span> </span>Eric Christopher [<a href="mailto:echristo@gmail.com" style="color:purple;text-decoration:underline" target="_blank">mailto:echristo@gmail.com</a>]<span> </span><br><b>Sent:</b><span> </span>Saturday, July 04, 2015 22:10<br><b>To:</b><span> </span>Badouh, Asaf;<span> </span><a href="mailto:llvm-commits@cs.uiuc.edu" style="color:purple;text-decoration:underline" target="_blank">llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br><b>Subject:</b><span> </span>Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.<u></u><u></u></span></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><u></u> <u></u></div><div><p class="MsoNormal" style="margin:0cm 0cm 12pt;font-size:12pt;font-family:'Times New Roman',serif"><u></u> <u></u></p><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">On Thu, Jul 2, 2015 at 7:04 AM Badouh, Asaf <<a href="mailto:asaf.badouh@intel.com" style="color:purple;text-decoration:underline" target="_blank">asaf.badouh@intel.com</a>> wrote:<u></u><u></u></div></div><blockquote style="border-style:none none none solid;border-left-color:rgb(204,204,204);border-left-width:1pt;padding:0cm 0cm 0cm 6pt;margin-left:4.8pt;margin-right:0cm"><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">The registers are not always zmm, they might be xmm/ymm as well.</span><u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">Same for the K masks, not always exists.</span><u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">That’s why we thought the best way is to check the prefix.</span><u></u><u></u></div></div></div></blockquote><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">Sure, but let's say you're implementing an assembler, how do you know which encoding to use if you get one using xmm/ymm and no k mask?<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><u></u> <u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">If you'll always want to use the avx512 encoding it seems a little wasteful, but you could also verify that you're assembling correctly via an MC test. If you'll want to base it upon the existence of the register or a k mask then you can do that by checking the assembly and not the encoding.<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><u></u> <u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">I could be missing something though? :)<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><u></u> <u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">-eric<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><blockquote style="border-style:none none none solid;border-left-color:rgb(204,204,204);border-left-width:1pt;padding:0cm 0cm 0cm 6pt;margin-left:4.8pt;margin-right:0cm"><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">-Asaf</span><u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><a name="14e64f24df3082e5_msg-f:1505593521080878408__MailEndCompos"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"> </span></a><u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><b><span style="font-size:11pt;font-family:Calibri,sans-serif">From:</span></b><span style="font-size:11pt;font-family:Calibri,sans-serif"><span> </span>Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" style="color:purple;text-decoration:underline" target="_blank">echristo@gmail.com</a>]<span> </span><br><b>Sent:</b><span> </span>Thursday, July 02, 2015 00:56</span><u></u><u></u></div></div></div><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><span style="font-size:11pt;font-family:Calibri,sans-serif"><br><b>To:</b><span> </span>Badouh, Asaf;<span> </span><a href="mailto:llvm-commits@cs.uiuc.edu" style="color:purple;text-decoration:underline" target="_blank">llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br><b>Subject:</b><span> </span>Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.</span><u></u><u></u></div></div></div><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div><div><p class="MsoNormal" style="margin:0cm 0cm 12pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></p><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">On Sun, Jun 21, 2015 at 4:28 AM Badouh, Asaf <<a href="mailto:asaf.badouh@intel.com" style="color:purple;text-decoration:underline" target="_blank">asaf.badouh@intel.com</a>> wrote:<u></u><u></u></div></div><blockquote style="border-style:none none none solid;border-left-color:rgb(204,204,204);border-left-width:1pt;padding:0cm 0cm 0cm 6pt;margin:5pt 0cm 5pt 4.8pt"><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">Hey Eric,<u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">That part of the test is not new, it just moved from other part of the file.<u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">Anyway (ElenaD & I) agree, it will be better to keep the encoding part out of these tests.<u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">But we think we should keep the prefix of the encoding to make sure it’s generate AVX512 code. E.g:<u></u><u></u></div></div></div><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">+ ; CHECK: vpmaxsq {{.*}}encoding: [0x62<u></u><u></u></div></div></div><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">is that ok with you?<u></u><u></u></div></div></div></blockquote><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">Can't you just check the register here or whether or not the k mask exists? (I mean, for this instruction in particular it's always going to be avx512 so not an issue, but the general idea applies).<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">I guess if it's not deducible otherwise, sure, but I find it hard to believe it's completely unknowable from text.<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">-eric<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><blockquote style="border-style:none none none solid;border-left-color:rgb(204,204,204);border-left-width:1pt;padding:0cm 0cm 0cm 6pt;margin:5pt 0cm 5pt 4.8pt"><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">-Asaf<u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><a name="14e64f24df3082e5_msg-f:1505593521080878408_msg-f:15045871"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"> </span></a><u></u><u></u></div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><b><span style="font-size:11pt;font-family:Calibri,sans-serif">From:</span></b><span style="font-size:11pt;font-family:Calibri,sans-serif"><span> </span>Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" style="color:purple;text-decoration:underline" target="_blank">echristo@gmail.com</a>]<span> </span><br><b>Sent:</b><span> </span>Friday, June 19, 2015 03:55<br><b>To:</b><span> </span>Badouh, Asaf;<span> </span><a href="mailto:llvm-commits@cs.uiuc.edu" style="color:purple;text-decoration:underline" target="_blank">llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br><b>Subject:</b><span> </span>Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.</span><u></u><u></u></div></div></div><div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">Hi Asaf,<u></u><u></u></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">I have a question here:<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div><div><blockquote style="border-style:none none none solid;border-left-color:rgb(204,204,204);border-left-width:1pt;padding:0cm 0cm 0cm 6pt;margin:5pt 0cm 5pt 4.8pt"><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"><br>+<br>+define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {<br>+ ; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]<u></u><u></u></div></blockquote><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">Why are you checking the encoding of instructions in the CodeGen tests? This sort of thing belongs in the MC tests for the instructions. It looks like there are already encoding tests so I'm not sure what you're attempting to check here? You don't appear to be checking the actual operands to the instruction.<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">-eric<u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><div><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif"> <u></u><u></u></div></div><blockquote style="border-style:none none none solid;border-left-color:rgb(204,204,204);border-left-width:1pt;padding:0cm 0cm 0cm 6pt;margin:5pt 0cm 5pt 4.8pt"><div style="margin:0cm 0cm 0.0001pt;font-size:12pt;font-family:'Times New Roman',serif">+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0, <8 x i64> %a1,<br>+ <8 x i64>zeroinitializer, i8 -1)<br>+ ret <8 x i64> %res<br>+}<br>+declare <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>+<br>+define <16 x i32> @test_vpminud(<16 x i32> %a0, <16 x i32> %a1) {<br>+ ; CHECK: vpminud {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3b,0xc1]<br>+ %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %a0, <16 x i32> %a1,<br>+ <16 x i32>zeroinitializer, i16 -1)<br>+ ret <16 x i32> %res<br>+}<br>+declare <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>+<br>+define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {<br>+ ; CHECK: vpmaxsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3d,0xc1]<br>+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %a0, <16 x i32> %a1,<br>+ <16 x i32>zeroinitializer, i16 -1)<br>+ ret <16 x i32> %res<br>+}<br>+declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsd %zmm<br>+; CHECK: {%k1}<br>+define <16 x i32>@test_int_x86_avx512_mask_pmaxs_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>+ %res2 = add <16 x i32> %res, %res1<br>+ ret <16 x i32> %res2<br>+}<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsq %zmm<br>+; CHECK: {%k1}<br>+define <8 x i64>@test_int_x86_avx512_mask_pmaxs_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>+ %res2 = add <8 x i64> %res, %res1<br>+ ret <8 x i64> %res2<br>+}<br>+<br>+declare <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxud %zmm<br>+; CHECK: {%k1}<br>+define <16 x i32>@test_int_x86_avx512_mask_pmaxu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>+ %res2 = add <16 x i32> %res, %res1<br>+ ret <16 x i32> %res2<br>+}<br>+<br>+declare <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxuq %zmm<br>+; CHECK: {%k1}<br>+define <8 x i64>@test_int_x86_avx512_mask_pmaxu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>+ %res2 = add <8 x i64> %res, %res1<br>+ ret <8 x i64> %res2<br>+}<br>+<br>+declare <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminsd %zmm<br>+; CHECK: {%k1}<br>+define <16 x i32>@test_int_x86_avx512_mask_pmins_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>+ %res2 = add <16 x i32> %res, %res1<br>+ ret <16 x i32> %res2<br>+}<br>+<br>+declare <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminsq %zmm<br>+; CHECK: {%k1}<br>+define <8 x i64>@test_int_x86_avx512_mask_pmins_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>+ %res2 = add <8 x i64> %res, %res1<br>+ ret <8 x i64> %res2<br>+}<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminud %zmm<br>+; CHECK: {%k1}<br>+define <16 x i32>@test_int_x86_avx512_mask_pminu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>+ %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>+ %res2 = add <16 x i32> %res, %res1<br>+ ret <16 x i32> %res2<br>+}<br>+<br>+declare <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminuq %zmm<br>+; CHECK: {%k1}<br>+define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>+ %res = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>+ %res2 = add <8 x i64> %res, %res1<br>+ ret <8 x i64> %res2<br>+}<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll<br>URL:<span> </span><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bw-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=l2CfvWbH5zN6oCcS_BQGHT9gvjP9HJeuucNqMArPh6E&e=" style="color:purple;text-decoration:underline" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll Tue Jun 16 03:39:27 2015<br>@@ -788,3 +788,107 @@ define <32 x i16> @test_mask_subs_epu16_<br> }<br><br> declare <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>+<br>+declare <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsb %zmm<br>+; CHECK: {%k1}<br>+define <64 x i8>@test_int_x86_avx512_mask_pmaxs_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>+ %res2 = add <64 x i8> %res, %res1<br>+ ret <64 x i8> %res2<br>+}<br>+<br>+declare <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsw %zmm<br>+; CHECK: {%k1}<br>+define <32 x i16>@test_int_x86_avx512_mask_pmaxs_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>+ %res2 = add <32 x i16> %res, %res1<br>+ ret <32 x i16> %res2<br>+}<br>+<br>+declare <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxub %zmm<br>+; CHECK: {%k1}<br>+define <64 x i8>@test_int_x86_avx512_mask_pmaxu_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>+ %res2 = add <64 x i8> %res, %res1<br>+ ret <64 x i8> %res2<br>+}<br>+<br>+declare <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_512<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxuw %zmm<br>+; CHECK: {%k1}<br>+define <32 x i16>@test_int_x86_avx512_mask_pmaxu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>+ %res2 = add <32 x i16> %res, %res1<br>+ ret <32 x i16> %res2<br>+}<br>+<br>+declare <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminsb %zmm<br>+; CHECK: {%k1}<br>+define <64 x i8>@test_int_x86_avx512_mask_pmins_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>+ %res2 = add <64 x i8> %res, %res1<br>+ ret <64 x i8> %res2<br>+}<br>+<br>+declare <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminsw %zmm<br>+; CHECK: {%k1}<br>+define <32 x i16>@test_int_x86_avx512_mask_pmins_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>+ %res2 = add <32 x i16> %res, %res1<br>+ ret <32 x i16> %res2<br>+}<br>+<br>+declare <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminub %zmm<br>+; CHECK: {%k1}<br>+define <64 x i8>@test_int_x86_avx512_mask_pminu_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>+ %res = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>+ %res2 = add <64 x i8> %res, %res1<br>+ ret <64 x i8> %res2<br>+}<br>+<br>+declare <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_512<br>+; CHECK-NOT: call<br>+; CHECK: vpminuw %zmm<br>+; CHECK: {%k1}<br>+define <32 x i16>@test_int_x86_avx512_mask_pminu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>+ %res = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>+ %res2 = add <32 x i16> %res, %res1<br>+ ret <32 x i16> %res2<br>+}<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll<br>URL:<span> </span><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bwvl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=MtmaJB0CzZzn3oacEiXC67zfqRtscKdLRstzKzdNyIk&e=" style="color:purple;text-decoration:underline" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll Tue Jun 16 03:39:27 2015<br>@@ -2667,4 +2667,212 @@ define <32 x i8> @test_mask_subs_epu8_rm<br> ret <32 x i8> %res<br> }<br><br>-declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>\ No newline at end of file<br>+declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>+<br>+declare <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsb %xmm<br>+; CHECK: {%k1}<br>+define <16 x i8>@test_int_x86_avx512_mask_pmaxs_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br>+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2 ,i16 %mask)<br>+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i8> %res, %res1<br>+ ret <16 x i8> %res2<br>+}<br>+<br>+declare <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsb %ymm<br>+; CHECK: {%k1}<br>+define <32 x i8>@test_int_x86_avx512_mask_pmaxs_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>+ %res2 = add <32 x i8> %res, %res1<br>+ ret <32 x i8> %res2<br>+}<br>+<br>+declare <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsw %xmm<br>+; CHECK: {%k1}<br>+define <8 x i16>@test_int_x86_avx512_mask_pmaxs_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>+ %res2 = add <8 x i16> %res, %res1<br>+ ret <8 x i16> %res2<br>+}<br>+<br>+declare <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsw %ymm<br>+; CHECK: {%k1}<br>+define <16 x i16>@test_int_x86_avx512_mask_pmaxs_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i16> %res, %res1<br>+ ret <16 x i16> %res2<br>+}<br>+<br>+declare <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxub %xmm<br>+; CHECK: {%k1}<br>+define <16 x i8>@test_int_x86_avx512_mask_pmaxu_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2,i16 %mask) {<br>+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br>+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i8> %res, %res1<br>+ ret <16 x i8> %res2<br>+}<br>+<br>+declare <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxub %ymm<br>+; CHECK: {%k1}<br>+define <32 x i8>@test_int_x86_avx512_mask_pmaxu_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>+ %res2 = add <32 x i8> %res, %res1<br>+ ret <32 x i8> %res2<br>+}<br>+<br>+declare <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxuw %xmm<br>+; CHECK: {%k1}<br>+define <8 x i16>@test_int_x86_avx512_mask_pmaxu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>+ %res2 = add <8 x i16> %res, %res1<br>+ ret <8 x i16> %res2<br>+}<br>+<br>+declare <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxuw %ymm<br>+; CHECK: {%k1}<br>+define <16 x i16>@test_int_x86_avx512_mask_pmaxu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i16> %res, %res1<br>+ ret <16 x i16> %res2<br>+}<br>+<br>+declare <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminsb %xmm<br>+; CHECK: {%k1}<br>+define <16 x i8>@test_int_x86_avx512_mask_pmins_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br>+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br>+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i8> %res, %res1<br>+ ret <16 x i8> %res2<br>+}<br>+<br>+declare <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminsb %ymm<br>+; CHECK: {%k1}<br>+define <32 x i8>@test_int_x86_avx512_mask_pmins_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>+ %res2 = add <32 x i8> %res, %res1<br>+ ret <32 x i8> %res2<br>+}<br>+<br>+declare <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminsw %xmm<br>+; CHECK: {%k1}<br>+define <8 x i16>@test_int_x86_avx512_mask_pmins_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>+ %res2 = add <8 x i16> %res, %res1<br>+ ret <8 x i16> %res2<br>+}<br>+<br>+declare <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminsw %ymm<br>+; CHECK: {%k1}<br>+define <16 x i16>@test_int_x86_avx512_mask_pmins_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i16> %res, %res1<br>+ ret <16 x i16> %res2<br>+}<br>+<br>+declare <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminub %xmm<br>+; CHECK: {%k1}<br>+define <16 x i8>@test_int_x86_avx512_mask_pminu_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br>+ %res = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br>+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i8> %res, %res1<br>+ ret <16 x i8> %res2<br>+}<br>+<br>+declare <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminub %ymm<br>+; CHECK: {%k1}<br>+define <32 x i8>@test_int_x86_avx512_mask_pminu_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>+ %res = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>+ %res2 = add <32 x i8> %res, %res1<br>+ ret <32 x i8> %res2<br>+}<br>+<br>+declare <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminuw %xmm<br>+; CHECK: {%k1}<br>+define <8 x i16>@test_int_x86_avx512_mask_pminu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>+ %res = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>+ %res2 = add <8 x i16> %res, %res1<br>+ ret <8 x i16> %res2<br>+}<br>+<br>+declare <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminuw %ymm<br>+; CHECK: {%k1}<br>+define <16 x i16>@test_int_x86_avx512_mask_pminu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>+ %res = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>+ %res2 = add <16 x i16> %res, %res1<br>+ ret <16 x i16> %res2<br>+}<br><br>Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll<br>URL:<span> </span><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512vl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=zwhhFLV2ynU3ASlzxB54u4fXW6WuknAXsqatLJz0MFs&e=" style="color:purple;text-decoration:underline" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Tue Jun 16 03:39:27 2015<br>@@ -2586,4 +2586,212 @@ define <8 x float> @test_getexp_ps_256(<<br> %res = call <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 -1)<br> ret <8 x float> %res<br> }<br>-declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone<br>\ No newline at end of file<br>+declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone<br>+<br>+declare <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsd %xmm<br>+; CHECK: {%k1}<br>+define <4 x i32>@test_int_x86_avx512_mask_pmaxs_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br>+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2 ,i8 %mask)<br>+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i32> %res, %res1<br>+ ret <4 x i32> %res2<br>+}<br>+<br>+declare <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsd %ymm<br>+; CHECK: {%k1}<br>+define <8 x i32>@test_int_x86_avx512_mask_pmaxs_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>+ %res2 = add <8 x i32> %res, %res1<br>+ ret <8 x i32> %res2<br>+}<br>+<br>+declare <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsq %xmm<br>+; CHECK: {%k1}<br>+define <2 x i64>@test_int_x86_avx512_mask_pmaxs_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>+ %res2 = add <2 x i64> %res, %res1<br>+ ret <2 x i64> %res2<br>+}<br>+<br>+declare <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxsq %ymm<br>+; CHECK: {%k1}<br>+define <4 x i64>@test_int_x86_avx512_mask_pmaxs_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i64> %res, %res1<br>+ ret <4 x i64> %res2<br>+}<br>+<br>+declare <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxud %xmm<br>+; CHECK: {%k1}<br>+define <4 x i32>@test_int_x86_avx512_mask_pmaxu_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2,i8 %mask) {<br>+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br>+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i32> %res, %res1<br>+ ret <4 x i32> %res2<br>+}<br>+<br>+declare <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxud %ymm<br>+; CHECK: {%k1}<br>+define <8 x i32>@test_int_x86_avx512_mask_pmaxu_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>+ %res2 = add <8 x i32> %res, %res1<br>+ ret <8 x i32> %res2<br>+}<br>+<br>+declare <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_128<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxuq %xmm<br>+; CHECK: {%k1}<br>+define <2 x i64>@test_int_x86_avx512_mask_pmaxu_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>+ %res2 = add <2 x i64> %res, %res1<br>+ ret <2 x i64> %res2<br>+}<br>+<br>+declare <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_256<br>+; CHECK-NOT: call<br>+; CHECK: vpmaxuq %ymm<br>+; CHECK: {%k1}<br>+define <4 x i64>@test_int_x86_avx512_mask_pmaxu_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i64> %res, %res1<br>+ ret <4 x i64> %res2<br>+}<br>+<br>+declare <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminsd %xmm<br>+; CHECK: {%k1}<br>+define <4 x i32>@test_int_x86_avx512_mask_pmins_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br>+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br>+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i32> %res, %res1<br>+ ret <4 x i32> %res2<br>+}<br>+<br>+declare <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminsd %ymm<br>+; CHECK: {%k1}<br>+define <8 x i32>@test_int_x86_avx512_mask_pmins_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>+ %res2 = add <8 x i32> %res, %res1<br>+ ret <8 x i32> %res2<br>+}<br>+<br>+declare <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminsq %xmm<br>+; CHECK: {%k1}<br>+define <2 x i64>@test_int_x86_avx512_mask_pmins_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>+ %res2 = add <2 x i64> %res, %res1<br>+ ret <2 x i64> %res2<br>+}<br>+<br>+declare <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminsq %ymm<br>+; CHECK: {%k1}<br>+define <4 x i64>@test_int_x86_avx512_mask_pmins_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i64> %res, %res1<br>+ ret <4 x i64> %res2<br>+}<br>+<br>+declare <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminud %xmm<br>+; CHECK: {%k1}<br>+define <4 x i32>@test_int_x86_avx512_mask_pminu_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br>+ %res = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br>+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i32> %res, %res1<br>+ ret <4 x i32> %res2<br>+}<br>+<br>+declare <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminud %ymm<br>+; CHECK: {%k1}<br>+define <8 x i32>@test_int_x86_avx512_mask_pminu_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>+ %res = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>+ %res2 = add <8 x i32> %res, %res1<br>+ ret <8 x i32> %res2<br>+}<br>+<br>+declare <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_128<br>+; CHECK-NOT: call<br>+; CHECK: vpminuq %xmm<br>+; CHECK: {%k1}<br>+define <2 x i64>@test_int_x86_avx512_mask_pminu_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>+ %res = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>+ %res2 = add <2 x i64> %res, %res1<br>+ ret <2 x i64> %res2<br>+}<br>+<br>+declare <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>+<br>+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_256<br>+; CHECK-NOT: call<br>+; CHECK: vpminuq %ymm<br>+; CHECK: {%k1}<br>+define <4 x i64>@test_int_x86_avx512_mask_pminu_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>+ %res = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>+ %res2 = add <4 x i64> %res, %res1<br>+ ret <4 x i64> %res2<br>+}<br>\ No newline at end of file<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu" style="color:purple;text-decoration:underline" target="_blank">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" style="color:purple;text-decoration:underline" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><u></u><u></u></div></blockquote></div></div></div></div></div><div><p style="margin-right:0cm;margin-left:0cm;font-size:12pt;font-family:'Times New Roman',serif">---------------------------------------------------------------------<br>Intel Israel (74) Limited<u></u><u></u></p><p style="margin-right:0cm;margin-left:0cm;font-size:12pt;font-family:'Times New Roman',serif">This e-mail and any attachments may contain confidential material for<br>the sole use of the intended recipient(s). Any review or distribution<br>by others is strictly prohibited. If you are not the intended<br>recipient, please contact the sender and delete all copies.<u></u><u></u></p></div></blockquote></div></div></div></div><div><p style="margin-right:0cm;margin-left:0cm;font-size:12pt;font-family:'Times New Roman',serif">---------------------------------------------------------------------<br>Intel Israel (74) Limited<u></u><u></u></p><p style="margin-right:0cm;margin-left:0cm;font-size:12pt;font-family:'Times New Roman',serif">This e-mail and any attachments may contain confidential material for<br>the sole use of the intended recipient(s). Any review or distribution<br>by others is strictly prohibited. If you are not the intended<br>recipient, please contact the sender and delete all copies.<u></u><u></u></p></div></blockquote></div></div></div><p style="margin-right:0cm;margin-left:0cm;font-size:12pt;font-family:'Times New Roman',serif;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px">---------------------------------------------------------------------<br>Intel Israel (74) Limited</p><p style="margin-right:0cm;margin-left:0cm;font-size:12pt;font-family:'Times New Roman',serif;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px">This e-mail and any attachments may contain confidential material for<br>the sole use of the intended recipient(s). Any review or distribution<br>by others is strictly prohibited. If you are not the intended<br>recipient, please contact the sender and delete all copies.</p><span style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;float:none;display:inline!important">_______________________________________________</span><br style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px"><span style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;float:none;display:inline!important">llvm-commits mailing list</span><br style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px"><a href="mailto:llvm-commits@cs.uiuc.edu" style="color:purple;text-decoration:underline;font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px" target="_blank">llvm-commits@cs.uiuc.edu</a><br style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px"><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" style="color:purple;text-decoration:underline;font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px"></div></blockquote></div></div></div><br></div><br>_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
<br></blockquote></div><br></div></div>