[llvm] r241411 - [TargetLowering] StringRefize asm constraint getters.
Eric Christopher
echristo at gmail.com
Sun Jul 5 12:35:18 PDT 2015
Hey cool, thanks!
On Sun, Jul 5, 2015, 12:32 PM Benjamin Kramer <benny.kra at googlemail.com>
wrote:
> Author: d0k
> Date: Sun Jul 5 14:29:18 2015
> New Revision: 241411
>
> URL: http://llvm.org/viewvc/llvm-project?rev=241411&view=rev
> Log:
> [TargetLowering] StringRefize asm constraint getters.
>
> There is some functional change here because it changes target code from
> atoi(3) to StringRef::getAsInteger which has error checking. For valid
> constraints there should be no difference.
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetLowering.h
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
> llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
> llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h
> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
> llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
> llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
> llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
> llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
> llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
>
> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Sun Jul 5 14:29:18
> 2015
> @@ -2679,7 +2679,7 @@ public:
> SelectionDAG *DAG = nullptr) const;
>
> /// Given a constraint, return the type of constraint it is for this
> target.
> - virtual ConstraintType getConstraintType(const std::string &Constraint)
> const;
> + virtual ConstraintType getConstraintType(StringRef Constraint) const;
>
> /// Given a physical register constraint (e.g. {edx}), return the
> register
> /// number and the register class for the register.
> @@ -2692,10 +2692,9 @@ public:
> /// returns a register number of 0 and a null register class pointer.
> virtual std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint, MVT VT)
> const;
> + StringRef Constraint, MVT VT) const;
>
> - virtual unsigned
> - getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
> + virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)
> const {
> if (ConstraintCode == "i")
> return InlineAsm::Constraint_i;
> else if (ConstraintCode == "m")
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Jul 5
> 14:29:18 2015
> @@ -2105,9 +2105,8 @@ PerformDAGCombine(SDNode *N, DAGCombiner
> // Inline Assembler Implementation Methods
>
> //===----------------------------------------------------------------------===//
>
> -
> TargetLowering::ConstraintType
> -TargetLowering::getConstraintType(const std::string &Constraint) const {
> +TargetLowering::getConstraintType(StringRef Constraint) const {
> unsigned S = Constraint.size();
>
> if (S == 1) {
> @@ -2140,7 +2139,7 @@ TargetLowering::getConstraintType(const
> }
>
> if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
> - if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
> + if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
> return C_Memory;
> return C_Register;
> }
> @@ -2227,7 +2226,7 @@ void TargetLowering::LowerAsmOperandForC
>
> std::pair<unsigned, const TargetRegisterClass *>
> TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
> - const std::string
> &Constraint,
> + StringRef Constraint,
> MVT VT) const {
> if (Constraint.empty() || Constraint[0] != '{')
> return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Sun Jul 5
> 14:29:18 2015
> @@ -4232,7 +4232,7 @@ bool AArch64TargetLowering::isFPImmLegal
> /// getConstraintType - Given a constraint letter, return the type of
> /// constraint it is for this target.
> AArch64TargetLowering::ConstraintType
> -AArch64TargetLowering::getConstraintType(const std::string &Constraint)
> const {
> +AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> default:
> @@ -4283,8 +4283,7 @@ AArch64TargetLowering::getSingleConstrai
>
> std::pair<unsigned, const TargetRegisterClass *>
> AArch64TargetLowering::getRegForInlineAsmConstraint(
> - const TargetRegisterInfo *TRI, const std::string &Constraint,
> - MVT VT) const {
> + const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> case 'r':
> @@ -4320,10 +4319,9 @@ AArch64TargetLowering::getRegForInlineAs
> unsigned Size = Constraint.size();
> if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
> tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
> - const std::string Reg =
> - std::string(&Constraint[2], &Constraint[Size - 1]);
> - int RegNo = atoi(Reg.c_str());
> - if (RegNo >= 0 && RegNo <= 31) {
> + int RegNo;
> + bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
> + if (!Failed && RegNo >= 0 && RegNo <= 31) {
> // v0 - v31 are aliases of q0 - q31.
> // By default we'll emit v0-v31 for this unless there's a
> modifier where
> // we'll emit the correct register as well.
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Sun Jul 5
> 14:29:18 2015
> @@ -471,8 +471,7 @@ private:
> std::vector<SDNode *> *Created) const override;
> bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
>
> - ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + ConstraintType getConstraintType(StringRef Constraint) const override;
> unsigned getRegisterByName(const char* RegName, EVT VT) const override;
>
> /// Examine constraint string and operand type and determine a weight
> value.
> @@ -483,14 +482,12 @@ private:
>
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
> void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
> std::vector<SDValue> &Ops,
> SelectionDAG &DAG) const override;
>
> - unsigned getInlineAsmMemConstraint(
> - const std::string &ConstraintCode) const override {
> + unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
> override {
> if (ConstraintCode == "Q")
> return InlineAsm::Constraint_Q;
> // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these
> are
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Sun Jul 5 14:29:18
> 2015
> @@ -2212,9 +2212,8 @@ SDValue SITargetLowering::CreateLiveInRe
>
> std::pair<unsigned, const TargetRegisterClass *>
> SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo
> *TRI,
> - const std::string
> &Constraint_,
> + StringRef Constraint,
> MVT VT) const {
> - StringRef Constraint(Constraint_);
> if (Constraint == "r") {
> switch(VT.SimpleTy) {
> default: llvm_unreachable("Unhandled type for 'r' inline asm
> constraint");
>
> Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h Sun Jul 5 14:29:18 2015
> @@ -114,9 +114,9 @@ public:
> SDLoc DL,
> SDValue Ptr) const;
>
> - std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(
> - const TargetRegisterInfo *TRI,
> - const std::string &Constraint, MVT VT)
> const override;
> + std::pair<unsigned, const TargetRegisterClass *>
> + getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> + StringRef Constraint, MVT VT) const
> override;
> SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V)
> const;
> };
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sun Jul 5 14:29:18 2015
> @@ -10664,7 +10664,7 @@ bool ARMTargetLowering::ExpandInlineAsm(
> /// getConstraintType - Given a constraint letter, return the type of
> /// constraint it is for this target.
> ARMTargetLowering::ConstraintType
> -ARMTargetLowering::getConstraintType(const std::string &Constraint) const
> {
> +ARMTargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> default: break;
> @@ -10723,10 +10723,8 @@ ARMTargetLowering::getSingleConstraintMa
> }
>
> typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
> -RCPair
> -ARMTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo
> *TRI,
> - const std::string
> &Constraint,
> - MVT VT) const {
> +RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
> + const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
> if (Constraint.size() == 1) {
> // GCC ARM Constraint Letters
> switch (Constraint[0]) {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Sun Jul 5 14:29:18 2015
> @@ -324,8 +324,7 @@ namespace llvm {
>
> bool ExpandInlineAsm(CallInst *CI) const override;
>
> - ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + ConstraintType getConstraintType(StringRef Constraint) const override;
>
> /// Examine constraint string and operand type and determine a weight
> value.
> /// The operand object must already have been set up with the operand
> type.
> @@ -334,8 +333,7 @@ namespace llvm {
>
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> /// LowerAsmOperandForConstraint - Lower the specified operand into
> the Ops
> /// vector. If it is invalid, don't add anything to Ops. If
> hasMemory is
> @@ -345,8 +343,8 @@ namespace llvm {
> std::vector<SDValue> &Ops,
> SelectionDAG &DAG) const override;
>
> - unsigned getInlineAsmMemConstraint(
> - const std::string &ConstraintCode) const override {
> + unsigned
> + getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
> if (ConstraintCode == "Q")
> return InlineAsm::Constraint_Q;
> else if (ConstraintCode.size() == 2) {
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Sun Jul 5
> 14:29:18 2015
> @@ -2338,8 +2338,7 @@ HexagonTargetLowering::EmitInstrWithCust
>
> std::pair<unsigned, const TargetRegisterClass *>
> HexagonTargetLowering::getRegForInlineAsmConstraint(
> - const TargetRegisterInfo *TRI, const std::string &Constraint,
> - MVT VT) const {
> + const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> case 'r': // R0-R31
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Sun Jul 5
> 14:29:18 2015
> @@ -179,11 +179,10 @@ bool isPositiveHalfWord(SDNode *N);
>
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> - unsigned getInlineAsmMemConstraint(
> - const std::string &ConstraintCode) const override {
> + unsigned
> + getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
> if (ConstraintCode == "o")
> return InlineAsm::Constraint_o;
> else if (ConstraintCode == "v")
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sun Jul 5
> 14:29:18 2015
> @@ -213,7 +213,7 @@ SDValue MSP430TargetLowering::LowerOpera
> /// getConstraintType - Given a constraint letter, return the type of
> /// constraint it is for this target.
> TargetLowering::ConstraintType
> -MSP430TargetLowering::getConstraintType(const std::string &Constraint)
> const {
> +MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> case 'r':
> @@ -227,8 +227,7 @@ MSP430TargetLowering::getConstraintType(
>
> std::pair<unsigned, const TargetRegisterClass *>
> MSP430TargetLowering::getRegForInlineAsmConstraint(
> - const TargetRegisterInfo *TRI, const std::string &Constraint,
> - MVT VT) const {
> + const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
> if (Constraint.size() == 1) {
> // GCC Constraint Letters
> switch (Constraint[0]) {
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h Sun Jul 5 14:29:18
> 2015
> @@ -96,11 +96,10 @@ namespace llvm {
> SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
>
> TargetLowering::ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + getConstraintType(StringRef Constraint) const override;
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> /// isTruncateFree - Return true if it's free to truncate a value of
> type
> /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value
> in
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sun Jul 5 14:29:18
> 2015
> @@ -3198,9 +3198,8 @@ MipsTargetLowering::LowerReturn(SDValue
>
> /// getConstraintType - Given a constraint letter, return the type of
> /// constraint it is for this target.
> -MipsTargetLowering::ConstraintType MipsTargetLowering::
> -getConstraintType(const std::string &Constraint) const
> -{
> +MipsTargetLowering::ConstraintType
> +MipsTargetLowering::getConstraintType(StringRef Constraint) const {
> // Mips specific constraints
> // GCC config/mips/constraints.md
> //
> @@ -3290,9 +3289,8 @@ MipsTargetLowering::getSingleConstraintM
> /// into non-numeric and numeric parts (Prefix and Reg). The first
> boolean flag
> /// that is returned indicates whether parsing was successful. The second
> flag
> /// is true if the numeric part exists.
> -static std::pair<bool, bool>
> -parsePhysicalReg(StringRef C, std::string &Prefix,
> - unsigned long long &Reg) {
> +static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef
> &Prefix,
> + unsigned long long &Reg) {
> if (C.front() != '{' || C.back() != '}')
> return std::make_pair(false, false);
>
> @@ -3300,7 +3298,7 @@ parsePhysicalReg(StringRef C, std::strin
> StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
> I = std::find_if(B, E, std::ptr_fun(isdigit));
>
> - Prefix.assign(B, I - B);
> + Prefix = StringRef(B, I - B);
>
> // The second flag is set to false if no numeric characters were found.
> if (I == E)
> @@ -3316,7 +3314,7 @@ parseRegForInlineAsmConstraint(StringRef
> const TargetRegisterInfo *TRI =
> Subtarget.getRegisterInfo();
> const TargetRegisterClass *RC;
> - std::string Prefix;
> + StringRef Prefix;
> unsigned long long Reg;
>
> std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
> @@ -3332,7 +3330,7 @@ parseRegForInlineAsmConstraint(StringRef
> RC = TRI->getRegClass(Prefix == "hi" ?
> Mips::HI32RegClassID : Mips::LO32RegClassID);
> return std::make_pair(*(RC->begin()), RC);
> - } else if (Prefix.compare(0, 4, "$msa") == 0) {
> + } else if (Prefix.startswith("$msa")) {
> // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
>
> // No numeric characters follow the name.
> @@ -3390,7 +3388,7 @@ parseRegForInlineAsmConstraint(StringRef
> /// pointer.
> std::pair<unsigned, const TargetRegisterClass *>
> MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo
> *TRI,
> - const std::string
> &Constraint,
> + StringRef Constraint,
> MVT VT) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Sun Jul 5 14:29:18 2015
> @@ -478,8 +478,7 @@ namespace llvm {
> bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
> override;
>
> // Inline asm support
> - ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + ConstraintType getConstraintType(StringRef Constraint) const override;
>
> /// Examine constraint string and operand type and determine a weight
> value.
> /// The operand object must already have been set up with the operand
> type.
> @@ -493,8 +492,7 @@ namespace llvm {
>
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> /// LowerAsmOperandForConstraint - Lower the specified operand into
> the Ops
> /// vector. If it is invalid, don't add anything to Ops. If
> hasMemory is
> @@ -505,8 +503,8 @@ namespace llvm {
> std::vector<SDValue> &Ops,
> SelectionDAG &DAG) const override;
>
> - unsigned getInlineAsmMemConstraint(
> - const std::string &ConstraintCode) const override {
> + unsigned
> + getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
> if (ConstraintCode == "R")
> return InlineAsm::Constraint_R;
> else if (ConstraintCode == "ZC")
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Sun Jul 5 14:29:18
> 2015
> @@ -3772,7 +3772,7 @@ bool NVPTXTargetLowering::isLegalAddress
> /// getConstraintType - Given a constraint letter, return the type of
> /// constraint it is for this target.
> NVPTXTargetLowering::ConstraintType
> -NVPTXTargetLowering::getConstraintType(const std::string &Constraint)
> const {
> +NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> default:
> @@ -3794,7 +3794,7 @@ NVPTXTargetLowering::getConstraintType(c
>
> std::pair<unsigned, const TargetRegisterClass *>
> NVPTXTargetLowering::getRegForInlineAsmConstraint(const
> TargetRegisterInfo *TRI,
> - const std::string
> &Constraint,
> + StringRef Constraint,
> MVT VT) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h Sun Jul 5 14:29:18
> 2015
> @@ -468,12 +468,10 @@ public:
> return MVT::i1;
> }
>
> - ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + ConstraintType getConstraintType(StringRef Constraint) const override;
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> SDValue LowerFormalArguments(
> SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sun Jul 5 14:29:18
> 2015
> @@ -10691,7 +10691,7 @@ unsigned PPCTargetLowering::getPrefLoopA
> /// getConstraintType - Given a constraint, return the type of
> /// constraint it is for this target.
> PPCTargetLowering::ConstraintType
> -PPCTargetLowering::getConstraintType(const std::string &Constraint) const
> {
> +PPCTargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> default: break;
> @@ -10776,7 +10776,7 @@ PPCTargetLowering::getSingleConstraintMa
>
> std::pair<unsigned, const TargetRegisterClass *>
> PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo
> *TRI,
> - const std::string
> &Constraint,
> + StringRef Constraint,
> MVT VT) const {
> if (Constraint.size() == 1) {
> // GCC RS6000 Constraint Letters
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Sun Jul 5 14:29:18
> 2015
> @@ -519,8 +519,7 @@ namespace llvm {
> MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
> MachineBasicBlock *MBB) const;
>
> - ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + ConstraintType getConstraintType(StringRef Constraint) const override;
>
> /// Examine constraint string and operand type and determine a weight
> value.
> /// The operand object must already have been set up with the operand
> type.
> @@ -529,8 +528,7 @@ namespace llvm {
>
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> /// getByValTypeAlignment - Return the desired alignment for ByVal
> aggregate
> /// function arguments in the caller parameter area. This is the
> actual
> @@ -544,8 +542,8 @@ namespace llvm {
> std::vector<SDValue> &Ops,
> SelectionDAG &DAG) const override;
>
> - unsigned getInlineAsmMemConstraint(
> - const std::string &ConstraintCode) const override {
> + unsigned
> + getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
> if (ConstraintCode == "es")
> return InlineAsm::Constraint_es;
> else if (ConstraintCode == "o")
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Sun Jul 5 14:29:18
> 2015
> @@ -3065,7 +3065,7 @@ SparcTargetLowering::expandAtomicRMW(Mac
> /// getConstraintType - Given a constraint letter, return the type of
> /// constraint it is for this target.
> SparcTargetLowering::ConstraintType
> -SparcTargetLowering::getConstraintType(const std::string &Constraint)
> const {
> +SparcTargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> default: break;
> @@ -3139,7 +3139,7 @@ LowerAsmOperandForConstraint(SDValue Op,
>
> std::pair<unsigned, const TargetRegisterClass *>
> SparcTargetLowering::getRegForInlineAsmConstraint(const
> TargetRegisterInfo *TRI,
> - const std::string
> &Constraint,
> + StringRef Constraint,
> MVT VT) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Sun Jul 5 14:29:18
> 2015
> @@ -72,7 +72,7 @@ namespace llvm {
>
> const char *getTargetNodeName(unsigned Opcode) const override;
>
> - ConstraintType getConstraintType(const std::string &Constraint) const
> override;
> + ConstraintType getConstraintType(StringRef Constraint) const override;
> ConstraintWeight
> getSingleConstraintMatchWeight(AsmOperandInfo &info,
> const char *constraint) const override;
> @@ -82,8 +82,7 @@ namespace llvm {
> SelectionDAG &DAG) const override;
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
> override;
> MVT getScalarShiftAmountTy(EVT LHSTy) const override { return
> MVT::i32; }
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Sun Jul 5
> 14:29:18 2015
> @@ -544,7 +544,7 @@ bool SystemZTargetLowering::isTruncateFr
>
> //===----------------------------------------------------------------------===//
>
> TargetLowering::ConstraintType
> -SystemZTargetLowering::getConstraintType(const std::string &Constraint)
> const {
> +SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> case 'a': // Address register
> @@ -641,13 +641,14 @@ getSingleConstraintMatchWeight(AsmOperan
> // has already been verified. MC is the class associated with "t" and
> // Map maps 0-based register numbers to LLVM register numbers.
> static std::pair<unsigned, const TargetRegisterClass *>
> -parseRegisterNumber(const std::string &Constraint,
> - const TargetRegisterClass *RC, const unsigned *Map) {
> +parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
> + const unsigned *Map) {
> assert(*(Constraint.end()-1) == '}' && "Missing '}'");
> if (isdigit(Constraint[2])) {
> - std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
> - unsigned Index = atoi(Suffix.c_str());
> - if (Index < 16 && Map[Index])
> + unsigned Index;
> + bool Failed =
> + Constraint.slice(2, Constraint.size() - 1).getAsInteger(10,
> Index);
> + if (!Failed && Index < 16 && Map[Index])
> return std::make_pair(Map[Index], RC);
> }
> return std::make_pair(0U, nullptr);
> @@ -655,8 +656,7 @@ parseRegisterNumber(const std::string &C
>
> std::pair<unsigned, const TargetRegisterClass *>
> SystemZTargetLowering::getRegForInlineAsmConstraint(
> - const TargetRegisterInfo *TRI, const std::string &Constraint,
> - MVT VT) const {
> + const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
> if (Constraint.size() == 1) {
> // GCC Constraint Letters
> switch (Constraint[0]) {
> @@ -687,7 +687,7 @@ SystemZTargetLowering::getRegForInlineAs
> return std::make_pair(0U, &SystemZ::FP32BitRegClass);
> }
> }
> - if (Constraint[0] == '{') {
> + if (Constraint.size() > 0 && Constraint[0] == '{') {
> // We need to override the default register parsing for GPRs and FPRs
> // because the interpretation depends on VT. The internal names of
> // the registers are also different from the external names
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h Sun Jul 5
> 14:29:18 2015
> @@ -379,10 +379,9 @@ public:
> const char *getTargetNodeName(unsigned Opcode) const override;
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
> TargetLowering::ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + getConstraintType(StringRef Constraint) const override;
> TargetLowering::ConstraintWeight
> getSingleConstraintMatchWeight(AsmOperandInfo &info,
> const char *constraint) const override;
> @@ -391,8 +390,7 @@ public:
> std::vector<SDValue> &Ops,
> SelectionDAG &DAG) const override;
>
> - unsigned getInlineAsmMemConstraint(
> - const std::string &ConstraintCode) const override {
> + unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
> override {
> if (ConstraintCode.size() == 1) {
> switch(ConstraintCode[0]) {
> default:
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul 5 14:29:18 2015
> @@ -25164,7 +25164,7 @@ bool X86TargetLowering::ExpandInlineAsm(
> (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
> matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
> AsmPieces.clear();
> - const std::string &ConstraintsStr = IA->getConstraintString();
> + StringRef ConstraintsStr = IA->getConstraintString();
> SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
> array_pod_sort(AsmPieces.begin(), AsmPieces.end());
> if (clobbersFlagRegisters(AsmPieces))
> @@ -25178,7 +25178,7 @@ bool X86TargetLowering::ExpandInlineAsm(
> matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
> matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
> AsmPieces.clear();
> - const std::string &ConstraintsStr = IA->getConstraintString();
> + StringRef ConstraintsStr = IA->getConstraintString();
> SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
> array_pod_sort(AsmPieces.begin(), AsmPieces.end());
> if (clobbersFlagRegisters(AsmPieces))
> @@ -25205,7 +25205,7 @@ bool X86TargetLowering::ExpandInlineAsm(
> /// getConstraintType - Given a constraint letter, return the type of
> /// constraint it is for this target.
> X86TargetLowering::ConstraintType
> -X86TargetLowering::getConstraintType(const std::string &Constraint) const
> {
> +X86TargetLowering::getConstraintType(StringRef Constraint) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
> case 'R':
> @@ -25537,7 +25537,7 @@ void X86TargetLowering::LowerAsmOperandF
>
> std::pair<unsigned, const TargetRegisterClass *>
> X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo
> *TRI,
> - const std::string
> &Constraint,
> + StringRef Constraint,
> MVT VT) const {
> // First, see if this is a constraint that directly corresponds to an
> LLVM
> // register class.
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Jul 5 14:29:18 2015
> @@ -707,8 +707,7 @@ namespace llvm {
>
> bool ExpandInlineAsm(CallInst *CI) const override;
>
> - ConstraintType
> - getConstraintType(const std::string &Constraint) const override;
> + ConstraintType getConstraintType(StringRef Constraint) const override;
>
> /// Examine constraint string and operand type and determine a weight
> value.
> /// The operand object must already have been set up with the operand
> type.
> @@ -726,8 +725,8 @@ namespace llvm {
> std::vector<SDValue> &Ops,
> SelectionDAG &DAG) const override;
>
> - unsigned getInlineAsmMemConstraint(
> - const std::string &ConstraintCode) const override {
> + unsigned
> + getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
> if (ConstraintCode == "i")
> return InlineAsm::Constraint_i;
> else if (ConstraintCode == "o")
> @@ -745,8 +744,7 @@ namespace llvm {
> /// error, this returns a register number of 0.
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> /// Return true if the addressing mode represented
> /// by AM is legal for this target, for a load/store of the specified
> type.
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Sun Jul 5 14:29:18
> 2015
> @@ -1970,7 +1970,7 @@ XCoreTargetLowering::isLegalAddressingMo
>
> std::pair<unsigned, const TargetRegisterClass *>
> XCoreTargetLowering::getRegForInlineAsmConstraint(const
> TargetRegisterInfo *TRI,
> - const std::string
> &Constraint,
> + StringRef Constraint,
> MVT VT) const {
> if (Constraint.size() == 1) {
> switch (Constraint[0]) {
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Sun Jul 5 14:29:18
> 2015
> @@ -175,8 +175,7 @@ namespace llvm {
> // Inline asm support
> std::pair<unsigned, const TargetRegisterClass *>
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> - const std::string &Constraint,
> - MVT VT) const override;
> + StringRef Constraint, MVT VT) const
> override;
>
> // Expand specifics
> SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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