<p dir="ltr">Hey cool, thanks!</p>
<br><div class="gmail_quote"><div dir="ltr">On Sun, Jul 5, 2015, 12:32 PM Benjamin Kramer <<a href="mailto:benny.kra@googlemail.com">benny.kra@googlemail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: d0k<br>
Date: Sun Jul 5 14:29:18 2015<br>
New Revision: 241411<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D241411-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=Sy8n7cvFL3U6v9biYjyxTqcekTT_xckhzjOU7QlVto8&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=241411&view=rev</a><br>
Log:<br>
[TargetLowering] StringRefize asm constraint getters.<br>
<br>
There is some functional change here because it changes target code from<br>
atoi(3) to StringRef::getAsInteger which has error checking. For valid<br>
constraints there should be no difference.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/Target/TargetLowering.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br>
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h<br>
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp<br>
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcISelLowering.h<br>
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreISelLowering.h<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_Target_TargetLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=0LPqIE5vzmsKwNJE-3iGkyQayqDB6l-i5TUW9f9MbQY&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -2679,7 +2679,7 @@ public:<br>
SelectionDAG *DAG = nullptr) const;<br>
<br>
/// Given a constraint, return the type of constraint it is for this target.<br>
- virtual ConstraintType getConstraintType(const std::string &Constraint) const;<br>
+ virtual ConstraintType getConstraintType(StringRef Constraint) const;<br>
<br>
/// Given a physical register constraint (e.g. {edx}), return the register<br>
/// number and the register class for the register.<br>
@@ -2692,10 +2692,9 @@ public:<br>
/// returns a register number of 0 and a null register class pointer.<br>
virtual std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint, MVT VT) const;<br>
+ StringRef Constraint, MVT VT) const;<br>
<br>
- virtual unsigned<br>
- getInlineAsmMemConstraint(const std::string &ConstraintCode) const {<br>
+ virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {<br>
if (ConstraintCode == "i")<br>
return InlineAsm::Constraint_i;<br>
else if (ConstraintCode == "m")<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDAG_TargetLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=2_GxiZf2dFnypTdJKj0s5Iuga0jD4F02z6VU2thHPcA&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -2105,9 +2105,8 @@ PerformDAGCombine(SDNode *N, DAGCombiner<br>
// Inline Assembler Implementation Methods<br>
//===----------------------------------------------------------------------===//<br>
<br>
-<br>
TargetLowering::ConstraintType<br>
-TargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+TargetLowering::getConstraintType(StringRef Constraint) const {<br>
unsigned S = Constraint.size();<br>
<br>
if (S == 1) {<br>
@@ -2140,7 +2139,7 @@ TargetLowering::getConstraintType(const<br>
}<br>
<br>
if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {<br>
- if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"<br>
+ if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"<br>
return C_Memory;<br>
return C_Register;<br>
}<br>
@@ -2227,7 +2226,7 @@ void TargetLowering::LowerAsmOperandForC<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,<br>
- const std::string &Constraint,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
if (Constraint.empty() || Constraint[0] != '{')<br>
return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_AArch64_AArch64ISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=_KireHVBW1N5LlLQ0YNpFSMSZRWkWxKXOyQRV4yXazo&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -4232,7 +4232,7 @@ bool AArch64TargetLowering::isFPImmLegal<br>
/// getConstraintType - Given a constraint letter, return the type of<br>
/// constraint it is for this target.<br>
AArch64TargetLowering::ConstraintType<br>
-AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+AArch64TargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
default:<br>
@@ -4283,8 +4283,7 @@ AArch64TargetLowering::getSingleConstrai<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
AArch64TargetLowering::getRegForInlineAsmConstraint(<br>
- const TargetRegisterInfo *TRI, const std::string &Constraint,<br>
- MVT VT) const {<br>
+ const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
case 'r':<br>
@@ -4320,10 +4319,9 @@ AArch64TargetLowering::getRegForInlineAs<br>
unsigned Size = Constraint.size();<br>
if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&<br>
tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {<br>
- const std::string Reg =<br>
- std::string(&Constraint[2], &Constraint[Size - 1]);<br>
- int RegNo = atoi(Reg.c_str());<br>
- if (RegNo >= 0 && RegNo <= 31) {<br>
+ int RegNo;<br>
+ bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);<br>
+ if (!Failed && RegNo >= 0 && RegNo <= 31) {<br>
// v0 - v31 are aliases of q0 - q31.<br>
// By default we'll emit v0-v31 for this unless there's a modifier where<br>
// we'll emit the correct register as well.<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_AArch64_AArch64ISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=91u8C14qGIWnvworN4rFDl6pi8iMNAgbrPbmbQo6A7Y&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -471,8 +471,7 @@ private:<br>
std::vector<SDNode *> *Created) const override;<br>
bool combineRepeatedFPDivisors(unsigned NumUsers) const override;<br>
<br>
- ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ ConstraintType getConstraintType(StringRef Constraint) const override;<br>
unsigned getRegisterByName(const char* RegName, EVT VT) const override;<br>
<br>
/// Examine constraint string and operand type and determine a weight value.<br>
@@ -483,14 +482,12 @@ private:<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,<br>
std::vector<SDValue> &Ops,<br>
SelectionDAG &DAG) const override;<br>
<br>
- unsigned getInlineAsmMemConstraint(<br>
- const std::string &ConstraintCode) const override {<br>
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {<br>
if (ConstraintCode == "Q")<br>
return InlineAsm::Constraint_Q;<br>
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_AMDGPU_SIISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=9A6wuoLlF3B54RzoMDSxCZlDRQhe9nABWIS_HhF3QxE&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -2212,9 +2212,8 @@ SDValue SITargetLowering::CreateLiveInRe<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint_,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
- StringRef Constraint(Constraint_);<br>
if (Constraint == "r") {<br>
switch(VT.SimpleTy) {<br>
default: llvm_unreachable("Unhandled type for 'r' inline asm constraint");<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_AMDGPU_SIISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=dAugKz0-1KJFvUnchTBiVE2Z95042dKgjlkoy4RbgQs&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -114,9 +114,9 @@ public:<br>
SDLoc DL,<br>
SDValue Ptr) const;<br>
<br>
- std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(<br>
- const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint, MVT VT) const override;<br>
+ std::pair<unsigned, const TargetRegisterClass *><br>
+ getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
+ StringRef Constraint, MVT VT) const override;<br>
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const;<br>
};<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_ARM_ARMISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=VZmOZwBlZX1fGkoIwuYf5hglibSmqK8HWmsHWqrH-8o&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -10664,7 +10664,7 @@ bool ARMTargetLowering::ExpandInlineAsm(<br>
/// getConstraintType - Given a constraint letter, return the type of<br>
/// constraint it is for this target.<br>
ARMTargetLowering::ConstraintType<br>
-ARMTargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+ARMTargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
default: break;<br>
@@ -10723,10 +10723,8 @@ ARMTargetLowering::getSingleConstraintMa<br>
}<br>
<br>
typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;<br>
-RCPair<br>
-ARMTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const {<br>
+RCPair ARMTargetLowering::getRegForInlineAsmConstraint(<br>
+ const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
// GCC ARM Constraint Letters<br>
switch (Constraint[0]) {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_ARM_ARMISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=NSgUxWbVulpOF5b6eb0tafRrYcJNUxzzoSOde98dYrI&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -324,8 +324,7 @@ namespace llvm {<br>
<br>
bool ExpandInlineAsm(CallInst *CI) const override;<br>
<br>
- ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ ConstraintType getConstraintType(StringRef Constraint) const override;<br>
<br>
/// Examine constraint string and operand type and determine a weight value.<br>
/// The operand object must already have been set up with the operand type.<br>
@@ -334,8 +333,7 @@ namespace llvm {<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops<br>
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is<br>
@@ -345,8 +343,8 @@ namespace llvm {<br>
std::vector<SDValue> &Ops,<br>
SelectionDAG &DAG) const override;<br>
<br>
- unsigned getInlineAsmMemConstraint(<br>
- const std::string &ConstraintCode) const override {<br>
+ unsigned<br>
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {<br>
if (ConstraintCode == "Q")<br>
return InlineAsm::Constraint_Q;<br>
else if (ConstraintCode.size() == 2) {<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_Hexagon_HexagonISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=pUo_rjWAG_iR5ma_En5bHZKPOmCXNewlA2L3rArebMk&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -2338,8 +2338,7 @@ HexagonTargetLowering::EmitInstrWithCust<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
HexagonTargetLowering::getRegForInlineAsmConstraint(<br>
- const TargetRegisterInfo *TRI, const std::string &Constraint,<br>
- MVT VT) const {<br>
+ const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
case 'r': // R0-R31<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_Hexagon_HexagonISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=AlFBtCTP_PWKkhrbPssW5LbFvJaKj1AiKt-7a77fiZM&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -179,11 +179,10 @@ bool isPositiveHalfWord(SDNode *N);<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
- unsigned getInlineAsmMemConstraint(<br>
- const std::string &ConstraintCode) const override {<br>
+ unsigned<br>
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {<br>
if (ConstraintCode == "o")<br>
return InlineAsm::Constraint_o;<br>
else if (ConstraintCode == "v")<br>
<br>
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_MSP430_MSP430ISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=Xr2tDkBXB5AaCuQdCTmxcO_uac5tH8_JLnl9TIQNV5k&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -213,7 +213,7 @@ SDValue MSP430TargetLowering::LowerOpera<br>
/// getConstraintType - Given a constraint letter, return the type of<br>
/// constraint it is for this target.<br>
TargetLowering::ConstraintType<br>
-MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+MSP430TargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
case 'r':<br>
@@ -227,8 +227,7 @@ MSP430TargetLowering::getConstraintType(<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
MSP430TargetLowering::getRegForInlineAsmConstraint(<br>
- const TargetRegisterInfo *TRI, const std::string &Constraint,<br>
- MVT VT) const {<br>
+ const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
// GCC Constraint Letters<br>
switch (Constraint[0]) {<br>
<br>
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_MSP430_MSP430ISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=01yKg9km0KtB7srA2-_-97riCbZezhc6o_gebSD4Et4&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -96,11 +96,10 @@ namespace llvm {<br>
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;<br>
<br>
TargetLowering::ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ getConstraintType(StringRef Constraint) const override;<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
/// isTruncateFree - Return true if it's free to truncate a value of type<br>
/// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_Mips_MipsISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=UHCDilNE19iHz89Y26rh36cMIB_CWjJOzb9X73qeqEw&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -3198,9 +3198,8 @@ MipsTargetLowering::LowerReturn(SDValue<br>
<br>
/// getConstraintType - Given a constraint letter, return the type of<br>
/// constraint it is for this target.<br>
-MipsTargetLowering::ConstraintType MipsTargetLowering::<br>
-getConstraintType(const std::string &Constraint) const<br>
-{<br>
+MipsTargetLowering::ConstraintType<br>
+MipsTargetLowering::getConstraintType(StringRef Constraint) const {<br>
// Mips specific constraints<br>
// GCC config/mips/<a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__constraints.md&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=tFCZp33x5_u3mMUSRWiz8PTj8JTaRVAVILWKOWwuJzQ&e=" rel="noreferrer" target="_blank">constraints.md</a><br>
//<br>
@@ -3290,9 +3289,8 @@ MipsTargetLowering::getSingleConstraintM<br>
/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag<br>
/// that is returned indicates whether parsing was successful. The second flag<br>
/// is true if the numeric part exists.<br>
-static std::pair<bool, bool><br>
-parsePhysicalReg(StringRef C, std::string &Prefix,<br>
- unsigned long long &Reg) {<br>
+static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,<br>
+ unsigned long long &Reg) {<br>
if (C.front() != '{' || C.back() != '}')<br>
return std::make_pair(false, false);<br>
<br>
@@ -3300,7 +3298,7 @@ parsePhysicalReg(StringRef C, std::strin<br>
StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;<br>
I = std::find_if(B, E, std::ptr_fun(isdigit));<br>
<br>
- Prefix.assign(B, I - B);<br>
+ Prefix = StringRef(B, I - B);<br>
<br>
// The second flag is set to false if no numeric characters were found.<br>
if (I == E)<br>
@@ -3316,7 +3314,7 @@ parseRegForInlineAsmConstraint(StringRef<br>
const TargetRegisterInfo *TRI =<br>
Subtarget.getRegisterInfo();<br>
const TargetRegisterClass *RC;<br>
- std::string Prefix;<br>
+ StringRef Prefix;<br>
unsigned long long Reg;<br>
<br>
std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);<br>
@@ -3332,7 +3330,7 @@ parseRegForInlineAsmConstraint(StringRef<br>
RC = TRI->getRegClass(Prefix == "hi" ?<br>
Mips::HI32RegClassID : Mips::LO32RegClassID);<br>
return std::make_pair(*(RC->begin()), RC);<br>
- } else if (Prefix.compare(0, 4, "$msa") == 0) {<br>
+ } else if (Prefix.startswith("$msa")) {<br>
// Parse $msa(ir|csr|access|save|modify|request|map|unmap)<br>
<br>
// No numeric characters follow the name.<br>
@@ -3390,7 +3388,7 @@ parseRegForInlineAsmConstraint(StringRef<br>
/// pointer.<br>
std::pair<unsigned, const TargetRegisterClass *><br>
MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_Mips_MipsISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=9zYAGki_B53OoC1RZXbixVa9gRPfj_tc-HwBTLDLJT8&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -478,8 +478,7 @@ namespace llvm {<br>
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;<br>
<br>
// Inline asm support<br>
- ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ ConstraintType getConstraintType(StringRef Constraint) const override;<br>
<br>
/// Examine constraint string and operand type and determine a weight value.<br>
/// The operand object must already have been set up with the operand type.<br>
@@ -493,8 +492,7 @@ namespace llvm {<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops<br>
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is<br>
@@ -505,8 +503,8 @@ namespace llvm {<br>
std::vector<SDValue> &Ops,<br>
SelectionDAG &DAG) const override;<br>
<br>
- unsigned getInlineAsmMemConstraint(<br>
- const std::string &ConstraintCode) const override {<br>
+ unsigned<br>
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {<br>
if (ConstraintCode == "R")<br>
return InlineAsm::Constraint_R;<br>
else if (ConstraintCode == "ZC")<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_NVPTX_NVPTXISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=I8w5czaNIcpogvDtvF_KDwYZXRJRIorjgw_zkTrMqqQ&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -3772,7 +3772,7 @@ bool NVPTXTargetLowering::isLegalAddress<br>
/// getConstraintType - Given a constraint letter, return the type of<br>
/// constraint it is for this target.<br>
NVPTXTargetLowering::ConstraintType<br>
-NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
default:<br>
@@ -3794,7 +3794,7 @@ NVPTXTargetLowering::getConstraintType(c<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
<br>
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_NVPTX_NVPTXISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=cSsdWzVpLBCrR2IDuIAY6qV-8HVR2FxxtFhe62e9f1w&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -468,12 +468,10 @@ public:<br>
return MVT::i1;<br>
}<br>
<br>
- ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ ConstraintType getConstraintType(StringRef Constraint) const override;<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
SDValue LowerFormalArguments(<br>
SDValue Chain, CallingConv::ID CallConv, bool isVarArg,<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_PowerPC_PPCISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=FG5au2nz-8XDQQjhbNe3Y3WXFtcHdGLp61310anZE0M&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -10691,7 +10691,7 @@ unsigned PPCTargetLowering::getPrefLoopA<br>
/// getConstraintType - Given a constraint, return the type of<br>
/// constraint it is for this target.<br>
PPCTargetLowering::ConstraintType<br>
-PPCTargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+PPCTargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
default: break;<br>
@@ -10776,7 +10776,7 @@ PPCTargetLowering::getSingleConstraintMa<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
// GCC RS6000 Constraint Letters<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_PowerPC_PPCISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=u3Jg71VCKKZg3X0hJt9lqysbIyQSe7goGhKHylgaboA&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -519,8 +519,7 @@ namespace llvm {<br>
MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,<br>
MachineBasicBlock *MBB) const;<br>
<br>
- ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ ConstraintType getConstraintType(StringRef Constraint) const override;<br>
<br>
/// Examine constraint string and operand type and determine a weight value.<br>
/// The operand object must already have been set up with the operand type.<br>
@@ -529,8 +528,7 @@ namespace llvm {<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate<br>
/// function arguments in the caller parameter area. This is the actual<br>
@@ -544,8 +542,8 @@ namespace llvm {<br>
std::vector<SDValue> &Ops,<br>
SelectionDAG &DAG) const override;<br>
<br>
- unsigned getInlineAsmMemConstraint(<br>
- const std::string &ConstraintCode) const override {<br>
+ unsigned<br>
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {<br>
if (ConstraintCode == "es")<br>
return InlineAsm::Constraint_es;<br>
else if (ConstraintCode == "o")<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_Sparc_SparcISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=N2t6khfeUakPDhJCEbGSNw_difUU1TFAzhc5aDhHvZI&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -3065,7 +3065,7 @@ SparcTargetLowering::expandAtomicRMW(Mac<br>
/// getConstraintType - Given a constraint letter, return the type of<br>
/// constraint it is for this target.<br>
SparcTargetLowering::ConstraintType<br>
-SparcTargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+SparcTargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
default: break;<br>
@@ -3139,7 +3139,7 @@ LowerAsmOperandForConstraint(SDValue Op,<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_Sparc_SparcISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=zW_L_1DmbH6Z1azx5xqAfZJ6zFhFsYSYeojKinAeFnQ&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -72,7 +72,7 @@ namespace llvm {<br>
<br>
const char *getTargetNodeName(unsigned Opcode) const override;<br>
<br>
- ConstraintType getConstraintType(const std::string &Constraint) const override;<br>
+ ConstraintType getConstraintType(StringRef Constraint) const override;<br>
ConstraintWeight<br>
getSingleConstraintMatchWeight(AsmOperandInfo &info,<br>
const char *constraint) const override;<br>
@@ -82,8 +82,7 @@ namespace llvm {<br>
SelectionDAG &DAG) const override;<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;<br>
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_SystemZ_SystemZISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=Ymv4xdW3UevtKdcKFp14MnhvML5rvI0FE32NxdbaQzc&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -544,7 +544,7 @@ bool SystemZTargetLowering::isTruncateFr<br>
//===----------------------------------------------------------------------===//<br>
<br>
TargetLowering::ConstraintType<br>
-SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+SystemZTargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
case 'a': // Address register<br>
@@ -641,13 +641,14 @@ getSingleConstraintMatchWeight(AsmOperan<br>
// has already been verified. MC is the class associated with "t" and<br>
// Map maps 0-based register numbers to LLVM register numbers.<br>
static std::pair<unsigned, const TargetRegisterClass *><br>
-parseRegisterNumber(const std::string &Constraint,<br>
- const TargetRegisterClass *RC, const unsigned *Map) {<br>
+parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,<br>
+ const unsigned *Map) {<br>
assert(*(Constraint.end()-1) == '}' && "Missing '}'");<br>
if (isdigit(Constraint[2])) {<br>
- std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);<br>
- unsigned Index = atoi(Suffix.c_str());<br>
- if (Index < 16 && Map[Index])<br>
+ unsigned Index;<br>
+ bool Failed =<br>
+ Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);<br>
+ if (!Failed && Index < 16 && Map[Index])<br>
return std::make_pair(Map[Index], RC);<br>
}<br>
return std::make_pair(0U, nullptr);<br>
@@ -655,8 +656,7 @@ parseRegisterNumber(const std::string &C<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
SystemZTargetLowering::getRegForInlineAsmConstraint(<br>
- const TargetRegisterInfo *TRI, const std::string &Constraint,<br>
- MVT VT) const {<br>
+ const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
// GCC Constraint Letters<br>
switch (Constraint[0]) {<br>
@@ -687,7 +687,7 @@ SystemZTargetLowering::getRegForInlineAs<br>
return std::make_pair(0U, &SystemZ::FP32BitRegClass);<br>
}<br>
}<br>
- if (Constraint[0] == '{') {<br>
+ if (Constraint.size() > 0 && Constraint[0] == '{') {<br>
// We need to override the default register parsing for GPRs and FPRs<br>
// because the interpretation depends on VT. The internal names of<br>
// the registers are also different from the external names<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_SystemZ_SystemZISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=ryiaAPsd87qMZtJleaFu8vx8QIW9HumLL_c6rPqwNpc&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -379,10 +379,9 @@ public:<br>
const char *getTargetNodeName(unsigned Opcode) const override;<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
TargetLowering::ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ getConstraintType(StringRef Constraint) const override;<br>
TargetLowering::ConstraintWeight<br>
getSingleConstraintMatchWeight(AsmOperandInfo &info,<br>
const char *constraint) const override;<br>
@@ -391,8 +390,7 @@ public:<br>
std::vector<SDValue> &Ops,<br>
SelectionDAG &DAG) const override;<br>
<br>
- unsigned getInlineAsmMemConstraint(<br>
- const std::string &ConstraintCode) const override {<br>
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {<br>
if (ConstraintCode.size() == 1) {<br>
switch(ConstraintCode[0]) {<br>
default:<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86ISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=JC2hYEBZiKKSEcI0Mxv_K_WgoaaWr6K-vDIDQSovlp8&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -25164,7 +25164,7 @@ bool X86TargetLowering::ExpandInlineAsm(<br>
(matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||<br>
matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {<br>
AsmPieces.clear();<br>
- const std::string &ConstraintsStr = IA->getConstraintString();<br>
+ StringRef ConstraintsStr = IA->getConstraintString();<br>
SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");<br>
array_pod_sort(AsmPieces.begin(), AsmPieces.end());<br>
if (clobbersFlagRegisters(AsmPieces))<br>
@@ -25178,7 +25178,7 @@ bool X86TargetLowering::ExpandInlineAsm(<br>
matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&<br>
matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {<br>
AsmPieces.clear();<br>
- const std::string &ConstraintsStr = IA->getConstraintString();<br>
+ StringRef ConstraintsStr = IA->getConstraintString();<br>
SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");<br>
array_pod_sort(AsmPieces.begin(), AsmPieces.end());<br>
if (clobbersFlagRegisters(AsmPieces))<br>
@@ -25205,7 +25205,7 @@ bool X86TargetLowering::ExpandInlineAsm(<br>
/// getConstraintType - Given a constraint letter, return the type of<br>
/// constraint it is for this target.<br>
X86TargetLowering::ConstraintType<br>
-X86TargetLowering::getConstraintType(const std::string &Constraint) const {<br>
+X86TargetLowering::getConstraintType(StringRef Constraint) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
case 'R':<br>
@@ -25537,7 +25537,7 @@ void X86TargetLowering::LowerAsmOperandF<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
// First, see if this is a constraint that directly corresponds to an LLVM<br>
// register class.<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86ISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=CHP_V_cwlbUjYANElgWGMu9rF0_09nSlLlZfKJy8Zg4&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -707,8 +707,7 @@ namespace llvm {<br>
<br>
bool ExpandInlineAsm(CallInst *CI) const override;<br>
<br>
- ConstraintType<br>
- getConstraintType(const std::string &Constraint) const override;<br>
+ ConstraintType getConstraintType(StringRef Constraint) const override;<br>
<br>
/// Examine constraint string and operand type and determine a weight value.<br>
/// The operand object must already have been set up with the operand type.<br>
@@ -726,8 +725,8 @@ namespace llvm {<br>
std::vector<SDValue> &Ops,<br>
SelectionDAG &DAG) const override;<br>
<br>
- unsigned getInlineAsmMemConstraint(<br>
- const std::string &ConstraintCode) const override {<br>
+ unsigned<br>
+ getInlineAsmMemConstraint(StringRef ConstraintCode) const override {<br>
if (ConstraintCode == "i")<br>
return InlineAsm::Constraint_i;<br>
else if (ConstraintCode == "o")<br>
@@ -745,8 +744,7 @@ namespace llvm {<br>
/// error, this returns a register number of 0.<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
/// Return true if the addressing mode represented<br>
/// by AM is legal for this target, for a load/store of the specified type.<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_XCore_XCoreISelLowering.cpp-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=YHJSKdB0cq_uO2wfyUk6kraGhvwYbMEhISY0EUV5lI0&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Sun Jul 5 14:29:18 2015<br>
@@ -1970,7 +1970,7 @@ XCoreTargetLowering::isLegalAddressingMo<br>
<br>
std::pair<unsigned, const TargetRegisterClass *><br>
XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
+ StringRef Constraint,<br>
MVT VT) const {<br>
if (Constraint.size() == 1) {<br>
switch (Constraint[0]) {<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_XCore_XCoreISelLowering.h-3Frev-3D241411-26r1-3D241410-26r2-3D241411-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=4szNgCnt-VY8WNMcdzWULza80px6ztPTsOCnm1EweoM&s=D5TOZjaM1lEKWWgb04_XM6BozENWWkOZlvFgy1OmZE8&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=241411&r1=241410&r2=241411&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Sun Jul 5 14:29:18 2015<br>
@@ -175,8 +175,7 @@ namespace llvm {<br>
// Inline asm support<br>
std::pair<unsigned, const TargetRegisterClass *><br>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,<br>
- const std::string &Constraint,<br>
- MVT VT) const override;<br>
+ StringRef Constraint, MVT VT) const override;<br>
<br>
// Expand specifics<br>
SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;<br>
<br>
<br>
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</blockquote></div>