[PATCH] [AArch64] Allow negative immediates for ADD/SUB in asm

[Renato Golin]

In http://reviews.llvm.org/D10810#196491, @t.p.northover wrote:

> Can't this be done as a simple InstAlias? The operand type even seems to exist already to support CodeGen (neg_addsub_shifted_imm, though it's a bit weird). You'd need a slightly adapted isNegAddSubImm and addNegAddSubImm methods, but you'd get your shifted values practically for free.


This was my first attempt, but since this is the asm parser, the instruction can be matched, but will not change. Both in asm files and inline asm, the parser is simply building MCInsts from whatever comes.

Unless I'm missing something obvious... Do you have an example in the table-gen file that does that already?


REPOSITORY
  rL LLVM

================
Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3324-3325
@@ +3323,4 @@
+    return 0;
+  // FIXME: Can we swap those?
+  case AArch64::ADDSWri:
+  case AArch64::ADDSXri:
----------------
t.p.northover wrote:
> The immediate form, we probably can. As I recall the edge cases where the transformation is invalid occur when the RHS is U?INT_(MIN|MAX). The shifted 12-bit immediates never are, so it should be OK.
Good point.

http://reviews.llvm.org/D10810

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/