[llvm] r239910 - [mips] [IAS] Add support for expanding LASym with a source register operand.

[Toma Tabacu]

Author: tomatabacu
Date: Wed Jun 17 09:31:51 2015
New Revision: 239910

URL: http://llvm.org/viewvc/llvm-project?rev=239910&view=rev
Log:
[mips] [IAS] Add support for expanding LASym with a source register operand.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9348

Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/test/MC/Mips/mips-expansions.s

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=239910&r1=239909&r2=239910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Jun 17 09:31:51 2015
@@ -186,9 +186,9 @@ class MipsAsmParser : public MCTargetAsm
                      bool Is32BitImm, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions);
 
-  bool loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
-                         bool Is32BitSym, SMLoc IDLoc,
-                         SmallVectorImpl<MCInst> &Instructions);
+  bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
+                               unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
+                               SmallVectorImpl<MCInst> &Instructions);
 
   bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions);
@@ -1929,18 +1929,20 @@ MipsAsmParser::expandLoadAddressReg(MCIn
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
+  const MCOperand &SrcRegOp = Inst.getOperand(1);
+  assert(SrcRegOp.isReg() && "expected register operand kind");
+
   const MCOperand &ImmOp = Inst.getOperand(2);
   assert((ImmOp.isImm() || ImmOp.isExpr()) &&
          "expected immediate operand kind");
   if (!ImmOp.isImm()) {
-    if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc,
-                          Instructions))
+    if (loadAndAddSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(),
+                                SrcRegOp.getReg(), Is32BitImm, IDLoc,
+                                Instructions))
       return true;
 
     return false;
   }
-  const MCOperand &SrcRegOp = Inst.getOperand(1);
-  assert(SrcRegOp.isReg() && "expected register operand kind");
 
   if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
                     Is32BitImm, IDLoc, Instructions))
@@ -1959,8 +1961,9 @@ MipsAsmParser::expandLoadAddressImm(MCIn
   assert((ImmOp.isImm() || ImmOp.isExpr()) &&
          "expected immediate operand kind");
   if (!ImmOp.isImm()) {
-    if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc,
-                          Instructions))
+    if (loadAndAddSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(),
+                                Mips::NoRegister, Is32BitImm, IDLoc,
+                                Instructions))
       return true;
 
     return false;
@@ -1973,9 +1976,9 @@ MipsAsmParser::expandLoadAddressImm(MCIn
   return false;
 }
 
-bool MipsAsmParser::loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
-                                      bool Is32BitSym, SMLoc IDLoc,
-                                      SmallVectorImpl<MCInst> &Instructions) {
+bool MipsAsmParser::loadAndAddSymbolAddress(
+    const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym,
+    SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
   warnIfNoMacro(IDLoc);
 
   if (Is32BitSym && isABI_N64())
@@ -2024,6 +2027,10 @@ bool MipsAsmParser::loadSymbolAddress(co
     createLShiftOri<0>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
                        Instructions);
   }
+
+  if (SrcReg != Mips::NoRegister)
+    createAddu(DstReg, DstReg, SrcReg, Instructions);
+
   return false;
 }
 

Modified: llvm/trunk/test/MC/Mips/mips-expansions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-expansions.s?rev=239910&r1=239909&r2=239910&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-expansions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-expansions.s Wed Jun 17 09:31:51 2015
@@ -43,6 +43,12 @@
 # CHECK:                             #   fixup A - offset: 0, value: symbol at ABS_HI, kind: fixup_Mips_HI16
 # CHECK: ori     $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35]
 # CHECK:                             #   fixup A - offset: 0, value: symbol at ABS_LO, kind: fixup_Mips_LO16
+  la $8, symbol($9)
+# CHECK: lui  $8, %hi(symbol)        # encoding: [A,A,0x08,0x3c]
+# CHECK:                             #   fixup A - offset: 0, value: symbol at ABS_HI, kind: fixup_Mips_HI16
+# CHECK: ori  $8, $8, %lo(symbol)    # encoding: [A,A,0x08,0x35]
+# CHECK:                             #   fixup A - offset: 0, value: symbol at ABS_LO, kind: fixup_Mips_LO16
+# CHECK: addu $8, $8, $9             # encoding: [0x21,0x40,0x09,0x01]
 
 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
   .set noat