[PATCH] Fix instruction scheduling live register tracking

[Paweł Bylica]

- Add LiveRegGen changes logs.


http://reviews.llvm.org/D9993

Files:
  lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
  test/CodeGen/X86/rrlist-livereg-corrutpion.ll

Index: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -537,6 +537,7 @@
              "interference on register dependence");
       LiveRegDefs[I->getReg()] = I->getSUnit();
       if (!LiveRegGens[I->getReg()]) {
+        DEBUG(dbgs() << "### LiveRegGen[" << I->getReg() << "] set to SU(" << SU->NodeNum << ")[" << SU->getHeight() << "]\n");
         ++NumLiveRegs;
         LiveRegGens[I->getReg()] = SU;
       }
@@ -742,6 +743,7 @@
     // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
     if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
       assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
+      DEBUG(dbgs() << "### LiveRegGen[" << I->getReg() << "] cleared off SU(" << LiveRegGens[I->getReg()]->NodeNum << ")[" << LiveRegGens[I->getReg()]->getHeight() << "]\n");
       --NumLiveRegs;
       LiveRegDefs[I->getReg()] = nullptr;
       LiveRegGens[I->getReg()] = nullptr;
@@ -813,6 +815,7 @@
       assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
       assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
              "Physical register dependency violated?");
+      DEBUG(dbgs() << "### LiveRegGen[" << I->getReg() << "] cleared off SU(" << SU->NodeNum << ")[" << SU->getHeight() << "]\n");
       --NumLiveRegs;
       LiveRegDefs[I->getReg()] = nullptr;
       LiveRegGens[I->getReg()] = nullptr;
@@ -851,14 +854,19 @@
   for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->isAssignedRegDep()) {
-      if (!LiveRegDefs[I->getReg()])
-        ++NumLiveRegs;
       // This becomes the nearest def. Note that an earlier def may still be
       // pending if this is a two-address node.
       LiveRegDefs[I->getReg()] = SU;
-      if (LiveRegGens[I->getReg()] == nullptr ||
-          I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
+      if (!LiveRegDefs[I->getReg()]) {
+        DEBUG(dbgs() << "### LiveRegGen[" << I->getReg() << "] set to SU(" << I->getSUnit()->NodeNum << ")[" << I->getSUnit()->getHeight() << "]\n");
+        ++NumLiveRegs;
         LiveRegGens[I->getReg()] = I->getSUnit();
+      } else if (I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()) {
+        DEBUG(dbgs() << "### LiveRegGen[" << I->getReg() << "] updated to SU(" << I->getSUnit()->NodeNum << ")[" << I->getSUnit()->getHeight() << "] from SU(" << LiveRegGens[I->getReg()]->NodeNum << ")[" << LiveRegGens[I->getReg()]->getHeight() << "]\n");
+        LiveRegGens[I->getReg()] = I->getSUnit();
+      } else {
+        DEBUG(dbgs() << "### LiveRegGen[" << I->getReg() << "] NOT UPDATED to SU(" << I->getSUnit()->NodeNum << ")[" << I->getSUnit()->getHeight() << "] from SU(" << LiveRegGens[I->getReg()]->NodeNum << ")[" << LiveRegGens[I->getReg()]->getHeight() << "]\n");
+      }
     }
   }
   if (SU->getHeight() < MinAvailableCycle)
Index: test/CodeGen/X86/rrlist-livereg-corrutpion.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/rrlist-livereg-corrutpion.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; CHECK-LABEL: test
+define i64 @test(i64 %a, i256 %b, i1 %c) {
+  %u = zext i64 %a to i256
+  %s = add i256 %u, 1
+  %o = trunc i256 %s to i1
+  %j = add i256 %s, 1
+  %i = icmp ule i64 %a, 1
+  %f = select i1 %o, i256 undef, i256 %j
+  %d = select i1 %i, i256 %f, i256 1
+  %e = add i256 %b, 1
+  %n = select i1 %c, i256 %e, i256 %b
+  %m = trunc i256 %n to i64
+  %h = add i64 %m, 1
+  %r = zext i64 %h to i256
+  %v = lshr i256 %d, %r
+  %t = trunc i256 %v to i1
+  %q = shl i256 1, %r
+  %p = and i256 %d, %q
+  %w = icmp ule i256 %n, 1
+  %y = select i1 %t, i256 undef, i256 %p
+  %x = select i1 %w, i256 %y, i256 %d
+  %z = trunc i256 %x to i64
+  ret i64 %z
+}

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