[PATCH] Patch to make AArch64 AsmParser be case insensitive about accepting vector register names

[Ranjeet Singh]

Hi James,

Thanks for the review.

Thanks,
Ranjeet

From: James Molloy [mailto:james at jamesmolloy.co.uk]
Sent: 08 June 2015 22:25
To: reviews+D10320+public+67e11b9caa35016c at reviews.llvm.org; Ranjeet Singh
Cc: kanheim at a-bix.com; llvm-commits at cs.uiuc.edu
Subject: Re: [PATCH] Patch to make AArch64 AsmParser be case insensitive about accepting vector register names

Hi Ranjeet,

This looks good to me.

Cheers,

James
On Mon, 8 Jun 2015 at 21:44, Ranjeet Singh <ranjeet.singh at arm.com<mailto:ranjeet.singh at arm.com>> wrote:
The AArch64 AsmParser doesn't accept vector register names that start with an upper-case 'V'. GAS is case insensitive about these register names and so is armasm, this patch will make armclang behave the same way.

http://reviews.llvm.org/D10320

Files:
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  test/MC/AArch64/case-insen-reg-names.s

Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1764,7 +1764,7 @@
 /// }

 static unsigned matchVectorRegName(StringRef Name) {
-  return StringSwitch<unsigned>(Name)
+  return StringSwitch<unsigned>(Name.lower())
       .Case("v0", AArch64::Q0)
       .Case("v1", AArch64::Q1)
       .Case("v2", AArch64::Q2)
Index: test/MC/AArch64/case-insen-reg-names.s
===================================================================
--- test/MC/AArch64/case-insen-reg-names.s
+++ test/MC/AArch64/case-insen-reg-names.s
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+
+fadd v0.2d, v5.2d, v6.2d
+fadd V0.2d, V5.2d, V6.2d
+fadd v0.2d, V5.2d, v6.2d
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/
_______________________________________________
llvm-commits mailing list
llvm-commits at cs.uiuc.edu<mailto:llvm-commits at cs.uiuc.edu>
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150608/cfdaae12/attachment.html>