[PATCH] [X86][SSE] Vectorized i8 and i16 shift operators

[Elena Demikhovsky]

REPOSITORY
  rL LLVM

================
Comment at: test/CodeGen/X86/avx2-vector-shifts.ll:274
@@ +273,3 @@
+
+define <16 x i16> @shl_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {
+; CHECK-LABEL:  shl_16i16
----------------
You can extend to 2 vectors of <8 x i32> and use variable shift left VPSLLVD.

================
Comment at: test/CodeGen/X86/vec_shift8.ll:201
@@ +200,3 @@
+;
+; SSE41:      movdqa    %xmm0, %xmm2
+; SSE41-NEXT: movdqa    %xmm1, %xmm0
----------------
extend to 2 vectors of <4 x i32> and use PSRAD instruction

http://reviews.llvm.org/D9474

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