[PATCH] [LLVM - ARM/AArch64] Add ACLE special register intrinsics (10.1)

[Luke Cheeseman]

================
Comment at: lib/Target/ARM/ARMISelDAGToDAG.cpp:3360
@@ +3359,3 @@
+  return StringSwitch<int>(RegString.lower())
+           .Case("r8_usr", 0x00)
+           .Case("r9_usr", 0x01)
----------------
rengolin wrote:
> Aren't there ARM::* register enums for those? You seem to be using a similar technique for VFP registers below, why can't you do the same for these?
The values here are masks for the MSR/MRS (Banked Register) instructions and not actual registers, as such there isn't an enum that I found for these values. Also, the values for VFP instructions aren't registers but opcodes, this is because the different registers get read/written from/to using VMRS/VMSR by creating SelctionDAG nodes with an opcode corresponding to the register. Thanks for highlighting this, I'll change the name of this function to better match what it is supposed to do and improve my comments around these.

http://reviews.llvm.org/D9699

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