[PATCH] [X86] Store DAGCombine should not assume arbitrary vector types are simple
Sanjay Patel
spatel at rotateright.com
Mon May 11 09:02:54 PDT 2015
Thanks, Michael. The code change LGTM, but can you minimize the test case and add it to the file with the related tests?
I think something like this patch would do:
Index: test/CodeGen/X86/i64-mem-copy.ll
===================================================================
--- test/CodeGen/X86/i64-mem-copy.ll (revision 236961)
+++ test/CodeGen/X86/i64-mem-copy.ll (working copy)
@@ -63,3 +63,15 @@
ret void
}
+; https://llvm.org/bugs/show_bug.cgi?id=23476
+; Handle extraction from a non-simple / pre-legalization type.
+
+define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) {
+; X32-LABEL: PR23476:
+; X32: movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT: movsd %xmm0, (%eax)
+ %ext = extractelement <5 x i64> %in, i32 %index
+ store i64 %ext, i64* %out, align 8
+ ret void
+}
+
http://reviews.llvm.org/D9659
EMAIL PREFERENCES
http://reviews.llvm.org/settings/panel/emailpreferences/
More information about the llvm-commits
mailing list