[PATCH] [X86] Store DAGCombine should not assume arbitrary vector types are simple

[Michael Kuperstein]

Hi spatel,

This fixes PR23476.
The basic issue is that we have a store being fed by an extract from v16i64. The combine tries to bitcast it into a v16f64, which is not a simple type, even though v16i64 is.
More generally, this may fire before legalization, so the origin type doesn't have to be simple either.

http://reviews.llvm.org/D9659

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/pr23476.ll

Index: test/CodeGen/X86/pr23476.ll
===================================================================
--- test/CodeGen/X86/pr23476.ll
+++ test/CodeGen/X86/pr23476.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -mattr=+avx | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+; Function Attrs: nounwind readnone
+declare double @log(double) #0
+
+; Function Attrs: nounwind readnone
+;declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) #0
+
+; Function Attrs: nounwind
+;declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) #1
+
+; Function Attrs: nounwind readnone
+;declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) #0
+
+; Function Attrs: nounwind readnone
+;declare i64 @llvm.cttz.i64(i64, i1) #0
+
+; CHECK-LABEL: f_v
+; CHECK: vmovsd  {{.*#+}} xmm0 = mem[0],zero
+; CHECK: vmovsd  %xmm0, (%esp)
+; Function Attrs: nounwind
+define void @f_v(float* noalias nocapture %RET) #1 {
+allocas:
+  br label %foreach_active_find_next.i
+
+foreach_active_find_next.i:                       ; preds = %foreach_active_find_next.i, %allocas
+  ;%extract.i.i.i = extractelement <16 x i64> <i64 4668012349850910720, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i32 undef
+  %extract.i.i.i = extractelement <14 x i64> <i64 4668012349850910720, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i32 undef
+  %int_to_double_bitcast.i.i.i41.i = bitcast i64 %extract.i.i.i to double
+  %r.i.i = tail call double @log(double %int_to_double_bitcast.i.i.i41.i) #1
+  br i1 undef, label %log___vyd.exit, label %foreach_active_find_next.i
+
+log___vyd.exit:                                   ; preds = %foreach_active_find_next.i
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 236935)"}
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -23188,7 +23188,7 @@
     SDValue OldExtract = St->getOperand(1);
     SDValue ExtOp0 = OldExtract.getOperand(0);
     unsigned VecSize = ExtOp0.getValueSizeInBits();
-    MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
+    EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
     SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
     SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
                                      BitCast, OldExtract.getOperand(1));

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