[llvm] r236569 - [ARM][FastISel] Use TST #1 instead of CMP #0 for select.
Ahmed Bougacha
ahmed.bougacha at gmail.com
Tue May 5 21:14:02 PDT 2015
Author: ab
Date: Tue May 5 23:14:02 2015
New Revision: 236569
URL: http://llvm.org/viewvc/llvm-project?rev=236569&view=rev
Log:
[ARM][FastISel] Use TST #1 instead of CMP #0 for select.
Since r234249, i1 are sext instead of zext; because of that, doing
"CMP rN, #0; IT EQ/NE" isn't correct anymore.
"TST #1" is the conservatively correct alternative - the tradeoff being
that it doesn't have a 16-bit encoding -, so use that instead.
Modified:
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=236569&r1=236568&r2=236569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue May 5 23:14:02 2015
@@ -1657,12 +1657,12 @@ bool ARMFastISel::SelectSelect(const Ins
if (Op2Reg == 0) return false;
}
- unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
- CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
+ unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
+ CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
AddOptionalDefs(
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
.addReg(CondReg)
- .addImm(0));
+ .addImm(1));
unsigned MovCCOpc;
const TargetRegisterClass *RC;
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll?rev=236569&r1=236568&r2=236569&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-select.ll Tue May 5 23:14:02 2015
@@ -7,12 +7,12 @@ define i32 @t1(i1 %c) nounwind readnone
entry:
; ARM: t1
; ARM: movw r{{[1-9]}}, #10
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
; ARM: moveq r{{[1-9]}}, #20
; ARM: mov r0, r{{[1-9]}}
; THUMB: t1
; THUMB: movs r{{[1-9]}}, #10
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: moveq r{{[1-9]}}, #20
; THUMB: mov r0, r{{[1-9]}}
@@ -23,11 +23,11 @@ entry:
define i32 @t2(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t2
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
; ARM: moveq r{{[1-9]}}, #20
; ARM: mov r0, r{{[1-9]}}
; THUMB: t2
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: moveq r{{[1-9]}}, #20
; THUMB: mov r0, r{{[1-9]}}
@@ -38,11 +38,11 @@ entry:
define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
entry:
; ARM: t3
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
; ARM: movne r2, r1
; ARM: add r0, r2, r1
; THUMB: t3
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
; THUMB: it ne
; THUMB: movne r2, r1
; THUMB: add.w r0, r2, r1
@@ -55,12 +55,12 @@ define i32 @t4(i1 %c) nounwind readnone
entry:
; ARM: t4
; ARM: mvn r{{[1-9]}}, #9
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #0
; ARM: mov r0, r{{[1-9]}}
; THUMB-LABEL: t4
; THUMB: mvn [[REG:r[1-9]+]], #9
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq [[REG]], #0
; THUMB: mov r0, [[REG]]
@@ -71,11 +71,11 @@ entry:
define i32 @t5(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t5
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #1
; ARM: mov r0, r{{[1-9]}}
; THUMB: t5
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq r{{[1-9]}}, #1
; THUMB: mov r0, r{{[1-9]}}
@@ -87,11 +87,11 @@ entry:
define i32 @t6(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t6
-; ARM: cmp r0, #0
+; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #978944
; ARM: mov r0, r{{[1-9]}}
; THUMB: t6
-; THUMB: cmp r0, #0
+; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq r{{[1-9]}}, #978944
; THUMB: mov r0, r{{[1-9]}}
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