[PATCH] Add VSX Scalar loads and stores to the PPC back end

[Bill Schmidt]

REPOSITORY
  rL LLVM

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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:100
@@ +99,3 @@
+
+    // VSX scalar loads introduced in ISA 2.07
+    let Predicates = [HasP8Vector] in {
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nemanjai wrote:
> kbarton wrote:
> > One general comment, more organizational then anything else. In PPCInstrAltivec.td, we chose to put all the P8 instructions together, at the end of the file, instead of intermixing them with existing instructions. Do we want to do the same thing in this file as well, if for no other reason then to be consistent?
> It is all the same to me. I just put them here because the loads/stores are here. I can just as easily move them. Are we all in agreement that this is what we want?
I agree with Kit; let's try to keep the P8Vector stuff together.

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Comment at: test/CodeGen/PowerPC/ppc64le-smallarg.ll:47
@@ -46,2 +46,3 @@
+; CHECK: lxsspx {{[0-9]+}}, {{[0-9]+}}, [[TOCREG]]
 ; CHECK: blr
 
----------------
nemanjai wrote:
> wschmidt wrote:
> > You don't have a run line specifying -mcpu, so this is potentially fragile.
> I can certainly put it in, but I avoided doing that for 2 reasons:
> 1. There is metadata in the test case identifying the target triple (which LLC respects) so the features are getting picked up due to the powerpc64le arch. This makes it work on other platforms too (tried on X86).
> 2. Since I didn't write the test case, I am not sure if the intent indeed was to not specify the -mcpu for some reason but rather provide the triple in the IR metadata.
> Please confirm that you would like me to remove the 
> ```
> target triple = "powerpc64le-unknown-linux-gnu"
> ```
> and add -mcpu=pwr8. I can then put back the original checks for other CPU's.
No, after reading your comments I'm okay with leaving it as is.  Relying on the arch for POWER8 is ok, but bear in mind that instructions for any follow-on ISA in the future won't be able to do this.

http://reviews.llvm.org/D9440

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