[PATCH] [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.

[Daniel Sanders]

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1822-1823
@@ +1821,4 @@
+    if (Bits31To16 == 0) {
+      createLShiftOri<32>(0, Reg, IDLoc, Instructions);
+      createLShiftOri<0>(Bits15To0, Reg, IDLoc, Instructions);
+    } else {
----------------
tomatabacu wrote:
> dsanders wrote:
> > Shouldn't this be:
> >   createLShiftOri<32>(Bits15To0, Reg, IDLoc, Instructions);
> > It looks like it will emit:
> >   dsll $Reg, $Reg, 32
> >   ori $Reg, $Reg, 0
> >   ori $Reg, $Reg, Bits15To0
> > at the moment.
> That's what it would have emitted in the past, but I recently added a check in createLShiftOri which prevents ORi of 0 to be emitted (rL235990).
> So, createLShiftOri<32>(0...) will only emit a DSLL of 32 (actually a DSLL32 of 0).
Ah yes, I see the guard now.

However, I still think it should be:
  createLShiftOri<32>(Bits15To0, Reg, IDLoc, Instructions);
just because it's a bit confusing to have one call that only emits a shift and one that only emits an ori.

http://reviews.llvm.org/D8974

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