[PATCH] [SelectionDAG] Unary vector constant folding integer legality fixes

Simon Pilgrim llvm-dev at redking.me.uk
Tue Apr 28 14:03:57 PDT 2015


Cleaned up crash test (to remove the autogen stink!)


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D9282

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  test/CodeGen/X86/fold-vector-bv-crash.ll
  test/CodeGen/X86/fold-vector-trunc-sitofp.ll

Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2858,27 +2858,46 @@
         // FIXME: Entirely reasonable to perform folding of other unary
         // operations here as the need arises.
         break;
-      case ISD::TRUNCATE:
-        // Constant build vector truncation can be done with the original scalar
-        // operands but with a new build vector with the truncated value type.
-        return getNode(ISD::BUILD_VECTOR, DL, VT, BV->ops());
       case ISD::FNEG:
       case ISD::FABS:
       case ISD::FCEIL:
       case ISD::FTRUNC:
       case ISD::FFLOOR:
       case ISD::FP_EXTEND:
+      case ISD::TRUNCATE:
       case ISD::UINT_TO_FP:
       case ISD::SINT_TO_FP: {
+        EVT SVT = VT.getScalarType();
+        EVT InVT = BV->getValueType(0);
+        EVT InSVT = InVT.getScalarType();
+
+        // Find legal integer scalar type for constant promotion.
+        EVT LegalSVT = SVT;
+        if (SVT.isInteger()) {
+          LegalSVT = TLI->getTypeToTransformTo(*getContext(), SVT);
+          assert(LegalSVT.bitsGE(SVT) && "Unexpected legal scalar type size");
+        }
+
         // Let the above scalar folding handle the folding of each element.
         SmallVector<SDValue, 8> Ops;
         for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
           SDValue OpN = BV->getOperand(i);
-          OpN = getNode(Opcode, DL, VT.getVectorElementType(), OpN);
+          EVT OpVT = OpN.getValueType();
+
+          // Build vector (integer) scalar operands may need implicit
+          // truncation - do this before constant folding.
+          if (OpVT.isInteger() && OpVT.bitsGT(InSVT))
+            OpN = getNode(ISD::TRUNCATE, DL, InSVT, OpN);
+
+          OpN = getNode(Opcode, DL, SVT, OpN);
           if (OpN.getOpcode() != ISD::UNDEF &&
               OpN.getOpcode() != ISD::Constant &&
               OpN.getOpcode() != ISD::ConstantFP)
             break;
+
+          // Legalize the (integer) scalar constant if necessary.
+          if (LegalSVT != SVT)
+            OpN = getNode(ISD::ANY_EXTEND, DL, LegalSVT, OpN);
           Ops.push_back(OpN);
         }
         if (Ops.size() == VT.getVectorNumElements())
Index: test/CodeGen/X86/fold-vector-bv-crash.ll
===================================================================
--- test/CodeGen/X86/fold-vector-bv-crash.ll
+++ test/CodeGen/X86/fold-vector-bv-crash.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=i686-unknown -mcpu=corei7
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7
+
+;
+; llvm-stress generated crash case due to build_vector implicit
+; truncation bug from constant folding after legalization.
+;
+
+ at G = external global i32
+
+define void @bv_crash_test() {
+  %I = insertelement <4 x i64> zeroinitializer, i64 15910, i32 0
+  %Tr = trunc <4 x i64> %I to <4 x i8>
+  %Bc = bitcast <4 x i8> %Tr to i32
+  store volatile i32 %Bc, i32* @G
+  ret void
+}
Index: test/CodeGen/X86/fold-vector-trunc-sitofp.ll
===================================================================
--- test/CodeGen/X86/fold-vector-trunc-sitofp.ll
+++ test/CodeGen/X86/fold-vector-trunc-sitofp.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s
+
+; Check that constant integer correctly being truncated before float conversion
+
+define <4 x float> @test1() {
+; CHECK-LABEL: test1
+; CHECK: vmovaps {{.*#+}} xmm0 = [-1.000000e+00,0.000000e+00,-1.000000e+00,0.000000e+00]
+; CHECK-NEXT: ret
+  %1 = trunc <4 x i3> <i3 -1, i3 -22, i3 7, i3 8> to <4 x i1>
+  %2 = sitofp <4 x i1> %1 to <4 x float>
+  ret <4 x float> %2
+}

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