[PATCH] X86: Do not select X86 custom vector nodes if operand types don't match

[Andrea Di Biagio]

Hi Matthias,
the patch looks good to me. I only added a very minor comment in the test (see below).

As a side note: I think that the major problem here is that the logic that matches horizontal add/sub operations is run as part of a target specific combine on BUILD_VECTOR nodes.
This is sub-optimal and may lead to a premature selection of target specific nodes.
As a long term fix, in bug 23296 I suggested to see if it is possible/reasonable to move all the horizontal add/sub selection logic from performBUILD_VECTORCombine in (a function called by) LowerBUILD_VECTOR.

Thanks,
Andrea


REPOSITORY
  rL LLVM

================
Comment at: test/CodeGen/X86/sse3-avx-addsub-2.ll:318
@@ -317,2 +317,3 @@
 
-
+define <2 x float> @test_v2f32(<2 x float> %v0, <2 x float> %v1) #0 {
+  %v2 = extractelement <2 x float> %v0, i32 0
----------------
You can remove the '#0'. That attribute set is not defined.

http://reviews.llvm.org/D9120

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