[PATCH] [AArch64] Rename v8.1a from "extension" to "architecture"

[James Molloy]

Hi Vlad,

I don't have any objections to this bikeshedding. Go ahead.

James

On Wed, 1 Apr 2015 at 14:12 Vladimir Sukharev <vladimir.sukharev at arm.com>
wrote:

> Hi jmolloy,
>
> v8.1a is renamed to architecture, accordingly to approaches in ARM backend.
> excess generic cpu is removed.
> Intended use: "generic" cpu with "v8.1a" subtarget feature
>
> Follow-up to http://reviews.llvm.org/rL233290
>
> REPOSITORY
>   rL LLVM
>
> http://reviews.llvm.org/D8766
>
> Files:
>   lib/Target/AArch64/AArch64.td
>   lib/Target/AArch64/AArch64InstrInfo.td
>   lib/Target/AArch64/AArch64Subtarget.cpp
>   lib/Target/AArch64/AArch64Subtarget.h
>
> Index: lib/Target/AArch64/AArch64.td
> ===================================================================
> --- lib/Target/AArch64/AArch64.td
> +++ lib/Target/AArch64/AArch64.td
> @@ -32,8 +32,8 @@
>  def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
>    "Enable ARMv8 CRC-32 checksum instructions">;
>
> -def FeatureV8_1a : SubtargetFeature<"v8.1a", "HasV8_1a", "true",
> -  "Enable ARMv8.1a extensions", [FeatureCRC]>;
> +def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
> +  "Support ARM v8.1a instructions", [FeatureCRC]>;
>
>  /// Cyclone has register move instructions which are "free".
>  def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove",
> "true",
> @@ -92,10 +92,6 @@
>                                                FeatureNEON,
>                                                FeatureCRC]>;
>
> -def : ProcessorModel<"generic-armv8.1-a", NoSchedModel, [FeatureV8_1a,
> -                                                         FeatureNEON,
> -                                                         FeatureCrypto]>;
> -
>  def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
>  def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
>  // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
> Index: lib/Target/AArch64/AArch64InstrInfo.td
> ===================================================================
> --- lib/Target/AArch64/AArch64InstrInfo.td
> +++ lib/Target/AArch64/AArch64InstrInfo.td
> @@ -22,8 +22,8 @@
>                                   AssemblerPredicate<"FeatureCrypto",
> "crypto">;
>  def HasCRC           : Predicate<"Subtarget->hasCRC()">,
>                                   AssemblerPredicate<"FeatureCRC", "crc">;
> -def HasV8_1a         : Predicate<"Subtarget->hasV8_1a()">,
> -                                 AssemblerPredicate<"FeatureV8_1a",
> "v8.1a">;
> +def HasV8_1a         : Predicate<"Subtarget->hasV8_1aOps()">,
> +                                 AssemblerPredicate<"HasV8_1aOps",
> "armv8.1a">;
>  def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
>  def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
>  def IsCyclone        : Predicate<"Subtarget->isCyclone()">;
> Index: lib/Target/AArch64/AArch64Subtarget.cpp
> ===================================================================
> --- lib/Target/AArch64/AArch64Subtarget.cpp
> +++ lib/Target/AArch64/AArch64Subtarget.cpp
> @@ -48,7 +48,7 @@
>                                     const TargetMachine &TM, bool
> LittleEndian)
>      : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
>        HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false),
> -      HasV8_1a(false), HasZeroCycleRegMove(false),
> HasZeroCycleZeroing(false),
> +      HasV8_1aOps(false), HasZeroCycleRegMove(false),
> HasZeroCycleZeroing(false),
>        IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT),
> FrameLowering(),
>        InstrInfo(initializeSubtargetDependencies(FS)),
>        TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
> Index: lib/Target/AArch64/AArch64Subtarget.h
> ===================================================================
> --- lib/Target/AArch64/AArch64Subtarget.h
> +++ lib/Target/AArch64/AArch64Subtarget.h
> @@ -41,7 +41,7 @@
>    bool HasNEON;
>    bool HasCrypto;
>    bool HasCRC;
> -  bool HasV8_1a;
> +  bool HasV8_1aOps;
>
>    // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
>    bool HasZeroCycleRegMove;
> @@ -101,7 +101,7 @@
>    bool hasNEON() const { return HasNEON; }
>    bool hasCrypto() const { return HasCrypto; }
>    bool hasCRC() const { return HasCRC; }
> -  bool hasV8_1a() const { return HasV8_1a; }
> +  bool hasV8_1aOps() const { return HasV8_1aOps; }
>
>    bool isLittleEndian() const { return IsLittle; }
>
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