<div dir="ltr">Hi Vlad,<br><br>I don't have any objections to this bikeshedding. Go ahead.<br><div><br></div><div>James</div></div><br><div class="gmail_quote">On Wed, 1 Apr 2015 at 14:12 Vladimir Sukharev <<a href="mailto:vladimir.sukharev@arm.com">vladimir.sukharev@arm.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi jmolloy,<br>
<br>
v8.1a is renamed to architecture, accordingly to approaches in ARM backend.<br>
excess generic cpu is removed.<br>
Intended use: "generic" cpu with "v8.1a" subtarget feature<br>
<br>
Follow-up to <a href="http://reviews.llvm.org/rL233290" target="_blank">http://reviews.llvm.org/<u></u>rL233290</a><br>
<br>
REPOSITORY<br>
rL LLVM<br>
<br>
<a href="http://reviews.llvm.org/D8766" target="_blank">http://reviews.llvm.org/D8766</a><br>
<br>
Files:<br>
lib/Target/AArch64/AArch64.td<br>
lib/Target/AArch64/<u></u>AArch64InstrInfo.td<br>
lib/Target/AArch64/<u></u>AArch64Subtarget.cpp<br>
lib/Target/AArch64/<u></u>AArch64Subtarget.h<br>
<br>
Index: lib/Target/AArch64/AArch64.td<br>
==============================<u></u>==============================<u></u>=======<br>
--- lib/Target/AArch64/AArch64.td<br>
+++ lib/Target/AArch64/AArch64.td<br>
@@ -32,8 +32,8 @@<br>
def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",<br>
"Enable ARMv8 CRC-32 checksum instructions">;<br>
<br>
-def FeatureV8_1a : SubtargetFeature<"v8.1a", "HasV8_1a", "true",<br>
- "Enable ARMv8.1a extensions", [FeatureCRC]>;<br>
+def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",<br>
+ "Support ARM v8.1a instructions", [FeatureCRC]>;<br>
<br>
/// Cyclone has register move instructions which are "free".<br>
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",<br>
@@ -92,10 +92,6 @@<br>
FeatureNEON,<br>
FeatureCRC]>;<br>
<br>
-def : ProcessorModel<"generic-armv8.<u></u>1-a", NoSchedModel, [FeatureV8_1a,<br>
- FeatureNEON,<br>
- FeatureCrypto]>;<br>
-<br>
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;<br>
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;<br>
// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.<br>
Index: lib/Target/AArch64/<u></u>AArch64InstrInfo.td<br>
==============================<u></u>==============================<u></u>=======<br>
--- lib/Target/AArch64/<u></u>AArch64InstrInfo.td<br>
+++ lib/Target/AArch64/<u></u>AArch64InstrInfo.td<br>
@@ -22,8 +22,8 @@<br>
AssemblerPredicate<"<u></u>FeatureCrypto", "crypto">;<br>
def HasCRC : Predicate<"Subtarget->hasCRC()<u></u>">,<br>
AssemblerPredicate<"<u></u>FeatureCRC", "crc">;<br>
-def HasV8_1a : Predicate<"Subtarget->hasV8_<u></u>1a()">,<br>
- AssemblerPredicate<"FeatureV8_<u></u>1a", "v8.1a">;<br>
+def HasV8_1a : Predicate<"Subtarget->hasV8_<u></u>1aOps()">,<br>
+ AssemblerPredicate<"HasV8_<u></u>1aOps", "armv8.1a">;<br>
def IsLE : Predicate<"Subtarget-><u></u>isLittleEndian()">;<br>
def IsBE : Predicate<"!Subtarget-><u></u>isLittleEndian()">;<br>
def IsCyclone : Predicate<"Subtarget-><u></u>isCyclone()">;<br>
Index: lib/Target/AArch64/<u></u>AArch64Subtarget.cpp<br>
==============================<u></u>==============================<u></u>=======<br>
--- lib/Target/AArch64/<u></u>AArch64Subtarget.cpp<br>
+++ lib/Target/AArch64/<u></u>AArch64Subtarget.cpp<br>
@@ -48,7 +48,7 @@<br>
const TargetMachine &TM, bool LittleEndian)<br>
: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),<br>
HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false),<br>
- HasV8_1a(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),<br>
+ HasV8_1aOps(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),<br>
IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),<br>
InstrInfo(<u></u>initializeSubtargetDependencie<u></u>s(FS)),<br>
TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}<br>
Index: lib/Target/AArch64/<u></u>AArch64Subtarget.h<br>
==============================<u></u>==============================<u></u>=======<br>
--- lib/Target/AArch64/<u></u>AArch64Subtarget.h<br>
+++ lib/Target/AArch64/<u></u>AArch64Subtarget.h<br>
@@ -41,7 +41,7 @@<br>
bool HasNEON;<br>
bool HasCrypto;<br>
bool HasCRC;<br>
- bool HasV8_1a;<br>
+ bool HasV8_1aOps;<br>
<br>
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.<br>
bool HasZeroCycleRegMove;<br>
@@ -101,7 +101,7 @@<br>
bool hasNEON() const { return HasNEON; }<br>
bool hasCrypto() const { return HasCrypto; }<br>
bool hasCRC() const { return HasCRC; }<br>
- bool hasV8_1a() const { return HasV8_1a; }<br>
+ bool hasV8_1aOps() const { return HasV8_1aOps; }<br>
<br>
bool isLittleEndian() const { return IsLittle; }<br>
<br>
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</blockquote></div>