[llvm] r233086 - [mips] Support 16-bit offsets for 'm' inline assembly memory constraint.
Daniel Sanders
daniel.sanders at imgtec.com
Tue Mar 24 08:19:14 PDT 2015
Author: dsanders
Date: Tue Mar 24 10:19:14 2015
New Revision: 233086
URL: http://llvm.org/viewvc/llvm-project?rev=233086&view=rev
Log:
[mips] Support 16-bit offsets for 'm' inline assembly memory constraint.
Reviewers: vkalintiris
Reviewed By: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8435
Added:
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=233086&r1=233085&r2=233086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Tue Mar 24 10:19:14 2015
@@ -948,11 +948,19 @@ SelectInlineAsmMemoryOperand(const SDVal
llvm_unreachable("Unexpected asm memory constraint");
// All memory constraints can at least accept raw pointers.
case InlineAsm::Constraint_i:
- case InlineAsm::Constraint_m:
case InlineAsm::Constraint_R:
OutOps.push_back(Op);
OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
return false;
+ case InlineAsm::Constraint_m:
+ if (selectAddrRegImm16(Op, Base, Offset)) {
+ OutOps.push_back(Base);
+ OutOps.push_back(Offset);
+ return false;
+ }
+ OutOps.push_back(Op);
+ OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
+ return false;
case InlineAsm::Constraint_ZC:
// ZC matches whatever the pref, ll, and sc instructions can handle for the
// given subtarget.
Added: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll?rev=233086&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll Tue Mar 24 10:19:14 2015
@@ -0,0 +1,61 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+ at data = global [8193 x i32] zeroinitializer
+
+define void @m(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @m_offset_4(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m_offset_4:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 4($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @m_offset_32764(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m_offset_32764:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 32764($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @m_offset_32768(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m_offset_32768:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK-DAG: ori $[[T0:[0-9]+]], $zero, 32768
+ ; CHECK: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR2]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=233086&r1=233085&r2=233086&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Tue Mar 24 10:19:14 2015
@@ -6,14 +6,13 @@
define i32 @f1(i32 %x) nounwind {
entry:
; CHECK-LABEL: f1:
-; CHECK: addiu $[[T0:[0-9]+]], $sp
; CHECK: #APP
-; CHECK: sw $4, 0($[[T0]])
+; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
; CHECK: #NO_APP
+; CHECK: lw $[[T1:[0-9]+]], %got(g1)
; CHECK: #APP
-; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
+; CHECK: lw $[[T3:[0-9]+]], [[OFFSET]]($sp)
; CHECK: #NO_APP
-; CHECK: lw $[[T1:[0-9]+]], %got(g1)
; CHECK: sw $[[T3]], 0($[[T1]])
%l1 = alloca i32, align 4
@@ -27,13 +26,13 @@ entry:
; "D": Second word of a double word. This works for any memory element
; double or single.
; CHECK: #APP
-; CHECK: lw ${{[0-9]+}},4(${{[0-9]+}});
+; CHECK: lw ${{[0-9]+}}, 16(${{[0-9]+}});
; CHECK: #NO_APP
; No "D": First word of a double word. This works for any memory element
; double or single.
; CHECK: #APP
-; CHECK: lw ${{[0-9]+}},0(${{[0-9]+}});
+; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}});
; CHECK: #NO_APP
@b = common global [20 x i32] zeroinitializer, align 4
@@ -41,8 +40,8 @@ entry:
define void @main() {
entry:
; Second word:
- tail call void asm sideeffect " lw $0,${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+ tail call void asm sideeffect " lw $0, ${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
; First word. Notice, no 'D':
- tail call void asm sideeffect " lw $0,${1};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+ tail call void asm sideeffect " lw $0, ${1};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
ret void
}
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