[PATCH] [X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus extract_subvector nodes.

[Quentin Colombet]

Hi Andrea,

Nice catch.

A small comment though.

Cheers,
-Quentin


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:9025
@@ -9024,3 +9024,3 @@
   if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1}) ||
       isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
     SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
----------------
I think it would be clearer to do something like:
bool UseOnlyV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
if (UseOnlyV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
<...>
 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
                                                 UseOnlyV1 ? V1 : V2, DAG.getIntPtrConstant(0));
<...>
}

http://reviews.llvm.org/D8259

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