[PATCH] [X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus extract_subvector nodes.

[Andrea Di Biagio]

Hi chandlerc, qcolombet, mkuper,

This patch fixes a bug in the shuffle lowering logic implemented by function 'lowerV2X128VectorShuffle'.

There are few cases where function 'lowerV2X128VectorShuffle' wrongly expands a shuffle of two v4X64 vectors into a CONCAT_VECTORS of two EXTRACT_SUBVECTOR nodes.
The problematic expansion only occurs when the shuffle mask M has an 'undef' element at position 2, and M is considered equivalent to mask <0,1,4,5>.
In that case only, the algorithm propagates the wrong vector to one of the two new EXTRACT_SUBVECTOR nodes.

Example:

```
define <4 x double> @test(<4 x double> %A, <4 x double> %B) {
entry:
  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 5>
  ret <4 x double> %0
}
```

Before this patch, llc (-mattr=+avx) generated:
  vinsertf128 $1, %xmm0, %ymm0, %ymm0

With this patch, llc correctly generates:
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

This bug was originally spotted by Greg Bedwell.

Added test lower-vec-shuffle-bug.ll.

Please let me know if ok to submit.

Thanks,
Andrea

http://reviews.llvm.org/D8259

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/lower-vec-shuffle-bug.ll

Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -9025,8 +9025,9 @@
       isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
     SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
                               DAG.getIntPtrConstant(0));
+    SDValue InVec = (Mask[2] == 4 || Mask[3] == 5) ? V2 : V1;
     SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
-                              Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
+                              InVec, DAG.getIntPtrConstant(0));
     return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
   }
   if (isShuffleEquivalent(V1, V2, Mask, {0, 1, 6, 7})) {
Index: test/CodeGen/X86/lower-vec-shuffle-bug.ll
===================================================================
--- test/CodeGen/X86/lower-vec-shuffle-bug.ll
+++ test/CodeGen/X86/lower-vec-shuffle-bug.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
+
+define <4 x double> @test1(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 5>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test2(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 5>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test4(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 1>
+  ret <4 x double> %0
+}

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