[PATCH] [SLSR] handle candidate form &B[i * S]

[Jingyue Wu]

Hi Andrew,

Thanks for the test!

That's because SLSR noticed main[main_stride] can be folded in an
addressing mode for thumbv7-apple-ios. Does this decision sound reasonable?
I don't know about this architecture. I changed the target triple to
"nvptx64-unknown-unknown" and SLSR started working.

Another complication is main_stride * 2 is rewritten to main_stride << 1
which is yet to be handled. I have a TODO on that. However, this shouldn't
affect %add.ptr4 in your test case.

Jingyue

On Tue, Mar 10, 2015 at 11:29 PM, Andrew Trick <atrick at apple.com> wrote:

>
> > On Mar 10, 2015, at 9:09 PM, Jingyue Wu <jingyue at google.com> wrote:
> >
> > Adds more comments and makes TTI mandatory
> >
> >
> > http://reviews.llvm.org/D7459
> >
> > Files:
> >  lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
> >  test/Transforms/StraightLineStrengthReduce/X86/lit.local.cfg
> >  test/Transforms/StraightLineStrengthReduce/X86/no-slsr.ll
> >  test/Transforms/StraightLineStrengthReduce/slsr-gep.ll
> >  test/Transforms/StraightLineStrengthReduce/slsr-mul.ll
> >  test/Transforms/StraightLineStrengthReduce/slsr.ll
> >
> > EMAIL PREFERENCES
> >  http://reviews.llvm.org/settings/panel/emailpreferences/
> > <D7459.21673.patch>
>
> I was wondering about the attached test case… can you comment on why your
> SLSR pass fails to find a basis for %mul3? It seems that your pass needs
> more than one address to be scaled using a mul or gep before it will
> optimize anything.
>
>   %mul1 = shl nsw i32 %main_stride, 1
>   %add.ptr2 = getelementptr inbounds i8, i8* %main, i32 %mul1
>   %4 = bitcast i8* %add.ptr2 to <1 x i64>*
>   %5 = load <1 x i64>, <1 x i64>* %4, align 8, !tbaa !4
>   %mul3 = mul nsw i32 %main_stride, 3
>   %add.ptr4 = getelementptr inbounds i8, i8* %main, i32 %mul3
>   %6 = bitcast i8* %add.ptr4 to <1 x i64>*
>   %7 = load <1 x i64>, <1 x i64>* %6, align 8, !tbaa !4
>
>
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