[PATCHES] R600/SI: New V_FRACT fix, intrinsic for S_FLBIT_I32, and more

Tue Mar 10 07:50:07 PDT 2015

On Thu, Mar 05, 2015 at 10:33:15PM +0100, Marek Olšák wrote:
> From e9f7ebe3fa7751e40b7d7cf4fadc17c7c8ef3a4a Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak at amd.com>
> Date: Sun, 1 Mar 2015 23:07:48 +0100
> Subject: [PATCH 2/3] R600/SI: Expand fract to floor, then only select V_FRACT
>  on CI
> 
> V_FRACT is buggy on SI.
> 
> R600-specific code is left intact.
> 
> v2: drop the multiclass, use complex VOP3 patterns
> ---
>  lib/Target/R600/AMDGPUISelLowering.cpp |  3 ---
>  lib/Target/R600/R600ISelLowering.cpp   |  4 +++
>  lib/Target/R600/SIISelLowering.cpp     |  6 +++++
>  lib/Target/R600/SIInstructions.td      | 22 +++++++++++++++++
>  test/CodeGen/R600/llvm.AMDGPU.fract.ll | 45 +++++++++++++++++++++++++++++++---
>  5 files changed, 73 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
> index 4707279..62a33fa 100644
> --- a/lib/Target/R600/AMDGPUISelLowering.cpp
> +++ b/lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -885,9 +885,6 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
>        return LowerIntrinsicIABS(Op, DAG);
>      case AMDGPUIntrinsic::AMDGPU_lrp:
>        return LowerIntrinsicLRP(Op, DAG);
> -    case AMDGPUIntrinsic::AMDGPU_fract:
> -    case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
> -      return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
>  
>      case AMDGPUIntrinsic::AMDGPU_clamp:
>      case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
> diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
> index c738611..cf0a60f 100644
> --- a/lib/Target/R600/R600ISelLowering.cpp
> +++ b/lib/Target/R600/R600ISelLowering.cpp
> @@ -837,6 +837,10 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
>      case Intrinsic::AMDGPU_rsq:
>        // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
>        return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
> +
> +    case AMDGPUIntrinsic::AMDGPU_fract:
> +    case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
> +      return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
>      }
>      // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
>      break;
> diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
> index 7d794b8..5c9a9f9 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -932,6 +932,12 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
>                         Op.getOperand(1),
>                         Op.getOperand(2),
>                         Op.getOperand(3));
> +
> +  case AMDGPUIntrinsic::AMDGPU_fract:
> +  case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
> +    return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
> +                       DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
> +
>    default:
>      return AMDGPUTargetLowering::LowerOperation(Op, DAG);
>    }
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index ab1f08f..6b9230a 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -3288,6 +3288,28 @@ def : Pat <
>    (V_CNDMASK_B32_e64 $src0, $src1, $src2)
>  >;
>  
> +//===----------------------------------------------------------------------===//
> +// Fract Patterns
> +//===----------------------------------------------------------------------===//
> +
> +let Predicates = [isCI] in {
> +
> +// Convert (x - floor(x)) to fract(x)
> +def : Pat <
> +  (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
> +             (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
> +  (V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
> +>;
> +
> +// Convert (x + (-floor(x))) to fract(x)
> +def : Pat <
> +  (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
> +             (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
> +  (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
> +>;
> +
> +} // End Predicates = [isCI]
> +

We are there different patterns for f32 and f64?  Also, can we match
this pattern on VI too?

>  //============================================================================//
>  // Miscellaneous Optimization Patterns
>  //============================================================================//
> diff --git a/test/CodeGen/R600/llvm.AMDGPU.fract.ll b/test/CodeGen/R600/llvm.AMDGPU.fract.ll
> index f4cf7fc..75f94e9 100644
> --- a/test/CodeGen/R600/llvm.AMDGPU.fract.ll
> +++ b/test/CodeGen/R600/llvm.AMDGPU.fract.ll
> @@ -1,14 +1,19 @@
> -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
> +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
> +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
>  ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
>  
> +declare float @llvm.fabs.f32(float  %Val)
>  declare float @llvm.AMDGPU.fract.f32(float) nounwind readnone
>  
>  ; Legacy name
>  declare float @llvm.AMDIL.fraction.f32(float) nounwind readnone
>  
>  ; FUNC-LABEL: {{^}}fract_f32:
> -; SI: v_fract_f32
> +; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
> +; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]]
> +; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
> +; GCN: buffer_store_dword [[RESULT]]
>  ; EG: FRACT
>  define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
>    %val = load float, float addrspace(1)* %src, align 4
> @@ -18,7 +23,10 @@ define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounw
>  }
>  
>  ; FUNC-LABEL: {{^}}fract_f32_legacy_amdil:
> -; SI: v_fract_f32
> +; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
> +; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]]
> +; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
> +; GCN: buffer_store_dword [[RESULT]]
>  ; EG: FRACT
>  define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
>    %val = load float, float addrspace(1)* %src, align 4
> @@ -26,3 +34,32 @@ define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)
>    store float %fract, float addrspace(1)* %out, align 4
>    ret void
>  }
> +
> +; FUNC-LABEL: {{^}}fract_f32_neg:
> +; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]]
> +; SI: v_floor_f32_e64 [[FLR:v[0-9]+]], -[[INPUT:v[0-9]+]]
> +; SI: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT]], [[FLR]]
> +; GCN: buffer_store_dword [[RESULT]]
> +; EG: FRACT
> +define void @fract_f32_neg(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
> +  %val = load float, float addrspace(1)* %src, align 4
> +  %neg = fsub float 0.0, %val
> +  %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone
> +  store float %fract, float addrspace(1)* %out, align 4
> +  ret void
> +}
> +
> +; FUNC-LABEL: {{^}}fract_f32_neg_abs:
> +; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT:v[0-9]+]]|
> +; SI: v_floor_f32_e64 [[FLR:v[0-9]+]], -|[[INPUT:v[0-9]+]]|
> +; SI: v_sub_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT]]|, [[FLR]]
> +; GCN: buffer_store_dword [[RESULT]]
> +; EG: FRACT
> +define void @fract_f32_neg_abs(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
> +  %val = load float, float addrspace(1)* %src, align 4
> +  %abs = call float @llvm.fabs.f32(float %val)
> +  %neg = fsub float 0.0, %abs
> +  %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone
> +  store float %fract, float addrspace(1)* %out, align 4
> +  ret void
> +}
> -- 
> 2.1.0
> 