[PATCH] [DagCombiner] Generalized BuildVector Vector Concatenation

[Aditya Nandakumar]

Hi 

I have a question with this patch.

Consider a DAG which looks like
v4i8 concat_vectors( v2i8 BUILD_VECTOR(i16 , i16),  v2i8 BUILD_VECTOR(i16, i16)). Consider that v2i8, v4i8 and i16 are legal types but i8 is not.

Previously, we would have picked the minimum type from
EVT SclTy0 = N0.getOperand(0)->getValueType(0);   
EVT SclTy1 = N1.getOperand(0)->getValueType(0);
EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
This would give us i16 as the MinType which is legal.

After the patch, this would pick 
MinType =VT.getScalarType()
which would be i8 and this would be illegal on the target.

I believe this happens after TypeLegalization. Is the transformation correct?

Thanks
Aditya


> On Feb 22, 2015, at 10:20 AM, Simon Pilgrim <llvm-dev at redking.me.uk> wrote:
> 
> Thanks Andrea
> 
> 
> REPOSITORY
>  rL LLVM
> 
> http://reviews.llvm.org/D7816
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