[llvm] r229608 - R600/SI: Fix encoding error from glc bit on VI SMRD instructions

[Matt Arsenault]

Author: arsenm
Date: Tue Feb 17 20:10:40 2015
New Revision: 229608

URL: http://llvm.org/viewvc/llvm-project?rev=229608&view=rev
Log:
R600/SI: Fix encoding error from glc bit on VI SMRD instructions

Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.td

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=229608&r1=229607&r2=229608&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Tue Feb 17 20:10:40 2015
@@ -576,7 +576,11 @@ multiclass SMRD_m <bits<5> op, string op
 
   def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
 
-  def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
+  // glc is only applicable to scalar stores, which are not yet
+  // implemented.
+  let glc = 0 in {
+    def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
+  }
 }
 
 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,