[llvm] r229607 - R600/SI: Fix operand encoding for flat instructions

Matt Arsenault Matthew.Arsenault at amd.com
Tue Feb 17 18:10:38 PST 2015


Author: arsenm
Date: Tue Feb 17 20:10:37 2015
New Revision: 229607

URL: http://llvm.org/viewvc/llvm-project?rev=229607&view=rev
Log:
R600/SI: Fix operand encoding for flat instructions

Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.td

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=229607&r1=229606&r2=229607&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Tue Feb 17 20:10:37 2015
@@ -1915,12 +1915,13 @@ multiclass MUBUF_Store_Helper <mubuf op,
 }
 
 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
-      FLAT <op, (outs regClass:$data),
+      FLAT <op, (outs regClass:$vdst),
                 (ins VReg_64:$addr),
-            asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
+            asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
   let glc = 0;
   let slc = 0;
   let tfe = 0;
+  let data = 0;
   let mayLoad = 1;
 }
 
@@ -1936,6 +1937,7 @@ class FLAT_Store_Helper <bits<7> op, str
   let glc = 0;
   let slc = 0;
   let tfe = 0;
+  let vdst = 0;
 }
 
 class MIMG_Mask <string op, int channels> {





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