[llvm] r229235 - R600/SI: Fix schedule model for v_div_scale_{f32|f64}

Matt Arsenault Matthew.Arsenault at amd.com
Fri Feb 13 20:03:18 PST 2015


Author: arsenm
Date: Fri Feb 13 22:03:18 2015
New Revision: 229235

URL: http://llvm.org/viewvc/llvm-project?rev=229235&view=rev
Log:
R600/SI: Fix schedule model for v_div_scale_{f32|f64}

Modified:
    llvm/trunk/lib/Target/R600/SIInstructions.td

Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=229235&r1=229234&r2=229235&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Fri Feb 13 22:03:18 2015
@@ -1735,9 +1735,11 @@ defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c
 
 } // isCommutable = 1, SchedRW = [WriteQuarterRate32]
 
+let SchedRW = [WriteFloatFMA, WriteSALU] in {
 defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d, 0x1e0>, "v_div_scale_f32", []>;
+}
 
-let SchedRW = [WriteDouble] in {
+let SchedRW = [WriteDouble, WriteSALU] in {
 // Double precision division pre-scale.
 defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>;
 } // let SchedRW = [WriteDouble]





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